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constraints v20 update, noted pins with true differential and clock capability

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and pins shared with WiFi and ADC
pull/3/head
Emard 6 years ago
parent f22eaf0d35
commit 38a2573d18
1 changed files with 44 additions and 42 deletions
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86
doc/constraints/ulx3s_v20.lpf
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@ -190,12 +190,12 @@ IOBUF PORT "ant_433mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
## Second USB port "US2" going directly into FPGA "usb", "ram" sheet ## Second USB port "US2" going directly into FPGA "usb", "ram" sheet
LOCATE COMP "usb_fpga_dp" SITE "E16"; # single ended or differential input only LOCATE COMP "usb_fpga_dp" SITE "E16"; # single ended or differential input only
LOCATE COMP "usb_fpga_dn" SITE "F16"; LOCATE COMP "usb_fpga_dn" SITE "F16";
IOBUF PORT "usb_fpga_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; IOBUF PORT "usb_fpga_dp" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16;
IOBUF PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; IOBUF PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16;
LOCATE COMP "usb_fpga_bd_dp" SITE "D15"; # differential bidirectional LOCATE COMP "usb_fpga_bd_dp" SITE "D15"; # single-ended bidirectional
LOCATE COMP "usb_fpga_bd_dn" SITE "E15"; LOCATE COMP "usb_fpga_bd_dn" SITE "E15";
IOBUF PORT "usb_fpga_bd_dp" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=4; IOBUF PORT "usb_fpga_bd_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "usb_fpga_bd_dn" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=4; IOBUF PORT "usb_fpga_bd_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "usb_fpga_pu_dp" SITE "B12"; # pull up/down control LOCATE COMP "usb_fpga_pu_dp" SITE "B12"; # pull up/down control
LOCATE COMP "usb_fpga_pu_dn" SITE "C12"; LOCATE COMP "usb_fpga_pu_dn" SITE "C12";
IOBUF PORT "usb_fpga_pu_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; IOBUF PORT "usb_fpga_pu_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
@ -328,12 +328,14 @@ IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
# gp[] (+) are used, gn[] (-) are ignored from design # gp[] (+) are used, gn[] (-) are ignored from design
# as they handle inverted signal by default. # as they handle inverted signal by default.
# To enable differential, rename LVCMOS33->LVCMOS33D # To enable differential, rename LVCMOS33->LVCMOS33D
LOCATE COMP "gp[0]" SITE "B11"; # J1_5+ GP0 # To enable clock i/o, add this (example):
LOCATE COMP "gn[0]" SITE "C11"; # J1_5- GN0 #FREQUENCY PORT "gp[12]" 25.00 MHZ;
LOCATE COMP "gp[1]" SITE "A10"; # J1_7+ GP1 LOCATE COMP "gp[0]" SITE "B11"; # J1_5+ GP0 PCLK
LOCATE COMP "gn[1]" SITE "A11"; # J1_7- GN1 LOCATE COMP "gn[0]" SITE "C11"; # J1_5- GN0 PCLK
LOCATE COMP "gp[2]" SITE "A9"; # J1_9+ GP2 LOCATE COMP "gp[1]" SITE "A10"; # J1_7+ GP1 PCLK
LOCATE COMP "gn[2]" SITE "B10"; # J1_9- GN2 LOCATE COMP "gn[1]" SITE "A11"; # J1_7- GN1 PCLK
LOCATE COMP "gp[2]" SITE "A9"; # J1_9+ GP2 GR_PCLK
LOCATE COMP "gn[2]" SITE "B10"; # J1_9- GN2 GR_PCLK
LOCATE COMP "gp[3]" SITE "B9"; # J1_11+ GP3 LOCATE COMP "gp[3]" SITE "B9"; # J1_11+ GP3
LOCATE COMP "gn[3]" SITE "C10"; # J1_11- GN3 LOCATE COMP "gn[3]" SITE "C10"; # J1_11- GN3
LOCATE COMP "gp[4]" SITE "A7"; # J1_13+ GP4 LOCATE COMP "gp[4]" SITE "A7"; # J1_13+ GP4
@ -359,17 +361,17 @@ IOBUF PORT "gn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "gp[7]" SITE "A6"; # J1_23+ GP7 LOCATE COMP "gp[7]" SITE "A6"; # J1_23+ GP7
LOCATE COMP "gn[7]" SITE "B6"; # J1_23- GN7 LOCATE COMP "gn[7]" SITE "B6"; # J1_23- GN7
LOCATE COMP "gp[8]" SITE "A4"; # J1_25+ GP8 LOCATE COMP "gp[8]" SITE "A4"; # J1_25+ GP8
LOCATE COMP "gn[8]" SITE "A5"; # J1_25- GN8 LOCATE COMP "gn[8]" SITE "A5"; # J1_25- GN8 DIFF
LOCATE COMP "gp[9]" SITE "A2"; # J1_27+ GP9 LOCATE COMP "gp[9]" SITE "A2"; # J1_27+ GP9 DIFF
LOCATE COMP "gn[9]" SITE "B1"; # J1_27- GN9 LOCATE COMP "gn[9]" SITE "B1"; # J1_27- GN9 DIFF
LOCATE COMP "gp[10]" SITE "C4"; # J1_29+ GP10 WIFI_GPIO27 LOCATE COMP "gp[10]" SITE "C4"; # J1_29+ GP10 DIFF
LOCATE COMP "gn[10]" SITE "B4"; # J1_29- GN10 LOCATE COMP "gn[10]" SITE "B4"; # J1_29- GN10 DIFF
LOCATE COMP "gp[11]" SITE "F4"; # J1_31+ GP11 WIFI_GPIO25 LOCATE COMP "gp[11]" SITE "F4"; # J1_31+ GP11 DIFF WIFI_GPIO26
LOCATE COMP "gn[11]" SITE "E3"; # J1_31- GN11 WIFI_GPIO26 LOCATE COMP "gn[11]" SITE "E3"; # J1_31- GN11 DIFF WIFI_GPIO25
LOCATE COMP "gp[12]" SITE "G3"; # J1_33+ GP12 WIFI_GPIO32 LOCATE COMP "gp[12]" SITE "G3"; # J1_33+ GP12 DIFF WIFI_GPIO33 PCLK
LOCATE COMP "gn[12]" SITE "F3"; # J1_33- GN12 WIFI_GPIO33 LOCATE COMP "gn[12]" SITE "F3"; # J1_33- GN12 DIFF WIFI_GPIO32 PCLK
LOCATE COMP "gp[13]" SITE "H4"; # J1_35+ GP13 WIFI_GPIO34 LOCATE COMP "gp[13]" SITE "H4"; # J1_35+ GP13 DIFF WIFI_GPIO35
LOCATE COMP "gn[13]" SITE "G5"; # J1_35- GN13 WIFI_GPIO35 LOCATE COMP "gn[13]" SITE "G5"; # J1_35- GN13 DIFF WIFI_GPIO34
IOBUF PORT "gp[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; IOBUF PORT "gp[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gn[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; IOBUF PORT "gn[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gp[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; IOBUF PORT "gp[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
@ -384,20 +386,20 @@ IOBUF PORT "gp[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gn[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; IOBUF PORT "gn[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gp[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; IOBUF PORT "gp[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gn[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; IOBUF PORT "gn[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "gp[14]" SITE "U18"; # J2_5+ GP14 LOCATE COMP "gp[14]" SITE "U18"; # J2_5+ GP14 DIFF ADC1
LOCATE COMP "gn[14]" SITE "U17"; # J2_5- GN14 LOCATE COMP "gn[14]" SITE "U17"; # J2_5- GN14 DIFF ADC0
LOCATE COMP "gp[15]" SITE "N17"; # J2_7+ GP15 LOCATE COMP "gp[15]" SITE "N17"; # J2_7+ GP15 DIFF ADC3
LOCATE COMP "gn[15]" SITE "P16"; # J2_7- GN15 LOCATE COMP "gn[15]" SITE "P16"; # J2_7- GN15 DIFF ADC2
LOCATE COMP "gp[16]" SITE "N16"; # J2_9+ GP16 LOCATE COMP "gp[16]" SITE "N16"; # J2_9+ GP16 DIFF ADC5
LOCATE COMP "gn[16]" SITE "M17"; # J2_9- GN16 LOCATE COMP "gn[16]" SITE "M17"; # J2_9- GN16 DIFF ADC4
LOCATE COMP "gp[17]" SITE "L16"; # J2_11+ GP17 LOCATE COMP "gp[17]" SITE "L16"; # J2_11+ GP17 DIFF ADC7 GR_PCLK
LOCATE COMP "gn[17]" SITE "L17"; # J2_11- GN17 LOCATE COMP "gn[17]" SITE "L17"; # J2_11- GN17 DIFF ADC6
LOCATE COMP "gp[18]" SITE "H18"; # J2_13+ GP18 LOCATE COMP "gp[18]" SITE "H18"; # J2_13+ GP18 DIFF
LOCATE COMP "gn[18]" SITE "H17"; # J2_13- GN18 LOCATE COMP "gn[18]" SITE "H17"; # J2_13- GN18 DIFF
LOCATE COMP "gp[19]" SITE "F17"; # J2_15+ GP19 LOCATE COMP "gp[19]" SITE "F17"; # J2_15+ GP19 DIFF
LOCATE COMP "gn[19]" SITE "G18"; # J2_15- GN19 LOCATE COMP "gn[19]" SITE "G18"; # J2_15- GN19 DIFF
LOCATE COMP "gp[20]" SITE "D18"; # J2_17+ GP20 LOCATE COMP "gp[20]" SITE "D18"; # J2_17+ GP20 DIFF
LOCATE COMP "gn[20]" SITE "E17"; # J2_17- GN20 LOCATE COMP "gn[20]" SITE "E17"; # J2_17- GN20 DIFF
IOBUF PORT "gp[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; IOBUF PORT "gp[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gn[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; IOBUF PORT "gn[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gp[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; IOBUF PORT "gp[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
@ -412,16 +414,16 @@ IOBUF PORT "gp[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gn[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; IOBUF PORT "gn[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gp[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; IOBUF PORT "gp[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gn[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; IOBUF PORT "gn[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "gp[21]" SITE "C18"; # J2_23+ GP21 LOCATE COMP "gp[21]" SITE "C18"; # J2_23+ GP21 DIFF
LOCATE COMP "gn[21]" SITE "D17"; # J2_23- GN21 LOCATE COMP "gn[21]" SITE "D17"; # J2_23- GN21 DIFF
LOCATE COMP "gp[22]" SITE "B15"; # J2_25+ GP22 D15->B15 LOCATE COMP "gp[22]" SITE "B15"; # J2_25+ GP22
LOCATE COMP "gn[22]" SITE "C15"; # J2_25- GN22 E15->C15 LOCATE COMP "gn[22]" SITE "C15"; # J2_25- GN22
LOCATE COMP "gp[23]" SITE "B17"; # J2_27+ GP23 LOCATE COMP "gp[23]" SITE "B17"; # J2_27+ GP23
LOCATE COMP "gn[23]" SITE "C17"; # J2_27- GN23 LOCATE COMP "gn[23]" SITE "C17"; # J2_27- GN23
LOCATE COMP "gp[24]" SITE "C16"; # J2_29+ GP24 LOCATE COMP "gp[24]" SITE "C16"; # J2_29+ GP24
LOCATE COMP "gn[24]" SITE "D16"; # J2_29- GN24 LOCATE COMP "gn[24]" SITE "D16"; # J2_29- GN24
LOCATE COMP "gp[25]" SITE "D14"; # J2_31+ GP25 B15->D14 LOCATE COMP "gp[25]" SITE "D14"; # J2_31+ GP25
LOCATE COMP "gn[25]" SITE "E14"; # J2_31- GN25 C15->E14 LOCATE COMP "gn[25]" SITE "E14"; # J2_31- GN25
LOCATE COMP "gp[26]" SITE "B13"; # J2_33+ GP26 LOCATE COMP "gp[26]" SITE "B13"; # J2_33+ GP26
LOCATE COMP "gn[26]" SITE "C13"; # J2_33- GN26 LOCATE COMP "gn[26]" SITE "C13"; # J2_33- GN26
LOCATE COMP "gp[27]" SITE "D13"; # J2_35+ GP27 LOCATE COMP "gp[27]" SITE "D13"; # J2_35+ GP27

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