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@ -155,4 +155,4 @@ Test the prototype.
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[ ] route 16-channel ADC
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[ ] route 16-channel ADC
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[x] move 8 LEDs a bit down and right
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[x] move 8 LEDs a bit down and right
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[x] let SD_CLK go to FPGA clock capable pin: swap SD_CLK and SD_D2 pins
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[x] let SD_CLK go to FPGA clock capable pin: swap SD_CLK and SD_D2 pins
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[ ] additional 2 differential lines for US2
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[x] additional 2 differential lines for US2
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