readme update

pull/3/head
Emard 7 years ago
parent 148611c2d7
commit 78e4a8ddbb

@ -155,4 +155,4 @@ Test the prototype.
[ ] route 16-channel ADC [ ] route 16-channel ADC
[x] move 8 LEDs a bit down and right [x] move 8 LEDs a bit down and right
[x] let SD_CLK go to FPGA clock capable pin: swap SD_CLK and SD_D2 pins [x] let SD_CLK go to FPGA clock capable pin: swap SD_CLK and SD_D2 pins
[ ] additional 2 differential lines for US2 [x] additional 2 differential lines for US2

Loading…
Cancel
Save