readme update

pull/3/head
davor 7 years ago
parent a293862950
commit f7dc501e2c

@ -154,5 +154,7 @@ Test the prototype.
[x] move 8 LEDs a bit down and right [x] move 8 LEDs a bit down and right
[x] let SD_CLK go to FPGA clock capable pin: swap SD_CLK and SD_D2 pins [x] let SD_CLK go to FPGA clock capable pin: swap SD_CLK and SD_D2 pins
[x] additional 2 differential lines for US2 [x] additional 2 differential lines for US2
[ ] additional US2 pins for pullup 1.5k and pulldown 15k [x] additional US2 pins for pullup 1.5k
[x] additional US2 pins for pull up-down 15k
[ ] unified US2 pullup/down: resistor-diode nework for pullup 1.5k and pulldown 15k
[ ] clear silkscreen mess with Cx under FPGA [ ] clear silkscreen mess with Cx under FPGA

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