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@ -154,5 +154,7 @@ Test the prototype.
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[x] move 8 LEDs a bit down and right
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[x] move 8 LEDs a bit down and right
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[x] let SD_CLK go to FPGA clock capable pin: swap SD_CLK and SD_D2 pins
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[x] let SD_CLK go to FPGA clock capable pin: swap SD_CLK and SD_D2 pins
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[x] additional 2 differential lines for US2
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[x] additional 2 differential lines for US2
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[ ] additional US2 pins for pullup 1.5k and pulldown 15k
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[x] additional US2 pins for pullup 1.5k
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[x] additional US2 pins for pull up-down 15k
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[ ] unified US2 pullup/down: resistor-diode nework for pullup 1.5k and pulldown 15k
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[ ] clear silkscreen mess with Cx under FPGA
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[ ] clear silkscreen mess with Cx under FPGA
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