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22a79ec617
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readme update
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6 years ago |
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readme update
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6 years ago |
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20d94f7e3e
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readme update
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6 years ago |
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readme update
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6 years ago |
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readme update
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6 years ago |
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aa176cae9f
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readme update
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6 years ago |
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a0d5476205
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readme update
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6 years ago |
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f976a0aaff
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readme update
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6 years ago |
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42c141a886
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readme update
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6 years ago |
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f7dc501e2c
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readme update
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6 years ago |
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davor
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a560d000d7
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feadme update
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6 years ago |
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Emard
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272eda6bb4
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readme update
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6 years ago |
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Emard
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78e4a8ddbb
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readme update
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6 years ago |
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davor
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017c797154
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readme update
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6 years ago |
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33440ee3fa
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schematics, readme: swap SD_CLK and SD_D2 pins,
now SD_CLK is connected to clock capable FPGA pin
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6 years ago |
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f9985ae004
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readme update
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6 years ago |
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readme update
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6 years ago |
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readme update
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6 years ago |
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readme update
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6 years ago |
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readme update
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6 years ago |
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readme update
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6 years ago |
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readme update
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6 years ago |
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34584d4156
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readme update
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6 years ago |
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448ac4f099
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readme update
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6 years ago |
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readme update
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6 years ago |
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3fb38e47a1
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readme update
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6 years ago |
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davor
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7cd2e904a5
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resolve merge conflict
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6 years ago |
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87095ae784
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readme and doc update
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6 years ago |
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Emard
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readme update
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6 years ago |
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Emard
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cae9d9685d
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readme update
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7 years ago |
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Emard
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13bcf60f39
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readme update
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7 years ago |
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Emard
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0fefc8839a
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readme update and some simple manual
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7 years ago |
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davor
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0556de6498
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readme update
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7 years ago |
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1696f5c161
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readme update
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7 years ago |
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readme and upgrade update
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7 years ago |
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readme and upgrading update
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7 years ago |
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c1cf614eb0
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readme update
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7 years ago |
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readme update
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7 years ago |
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readme update
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7 years ago |
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readme update
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7 years ago |
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5ae86e21bc
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readme update
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7 years ago |
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readme update, separated document for the PCB v1.7 upgrade
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7 years ago |
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readme update
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7 years ago |
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readme update
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7 years ago |
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7 years ago |
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readme update
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7 years ago |
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47fbd0ddbb
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readme update
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7 years ago |
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3a87d41201
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schematics: additional comments for wifi bootstrapping and readme update
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7 years ago |
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f5de9a85ed
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schematics: connecting SHUTDOWN to FPGA
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7 years ago |
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fdfc6525ea
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readme update
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7 years ago |
