c1053dd7bd
schematics: cleanup of MFG_PN to simplify BOM
7 years ago
6b50f65544
footprints: FPGA renaming Quad SPI lines D2,D3
...
schematics: reference FPGA footprint directly (not from rescue file)
7 years ago
987aefa1fd
schematics: routing FPGA to SPI QUAD.
...
BTN_R,U connected to BANK2,3 on "ram" sheet
7 years ago
e81d05b68d
schematics: renaming pins J..+- to GP,GN..
7 years ago
91dc09995c
schematics: SDRAM manufacturer url and PN
7 years ago
afdfad2fa2
schematics: comments about switching regulators
7 years ago
3a87d41201
schematics: additional comments for wifi bootstrapping and readme update
7 years ago
f5de9a85ed
schematics: connecting SHUTDOWN to FPGA
7 years ago
b41c200d79
schematics: cosmetics, hidign some button datasheet URL for schematics
7 years ago
537e2229b6
schematics: swap U2,U9
7 years ago
3915779e0c
schematics: part numbers and URLs of datasheets and manufacturers
...
of most chips and connectors. Small parts not done yet.
7 years ago
52814d6ae0
WIFI LED (blue) on schematics
7 years ago
4a35c95132
GPDI CEC add protection resistor R61 470 ohm
7 years ago
a5a51a8f28
connected missing SD card pins to esp-32
7 years ago
cca17d282d
open-close to check that everything loads fine
7 years ago
35b3a8b3dd
changing to 45F which is production device now
...
schem symbol 45F fixed typo T8->T7 (GND) and SERDES
7 years ago
1ffed1dea1
comment at "usb" sheet about reasons for the JTAG pinout
...
different than ULX2s
7 years ago
ba4c8e8d22
PCB v1.6 SDRAM fully reworked
7 years ago
1ea88bda53
Adding pins to schematic symbols for all chips in unit "H" (SERDES)
...
Non-serdes chips need GND connection on unit "H".
"power" sheet now connects GND's at unit "H".
7 years ago
e4fc99887e
moving GND and VCC on schematics symbols to
...
common locations for planned PCB which
supports upgrade path for example
12F->25F->45F->85F and if possible ECP5U->ECP5UM
7 years ago
1cdad1e4d0
all diodes SOD-323 and SOD-323F packages changed to handsoldering
...
(bigger pads, more reworkable)
silkscreen moving references GPDI1 and SW1 for readability
7 years ago
bc4b88ee58
Micro SD: using SCHD3A0100
7 years ago
f3d84dbfdc
LED D19 was oriented wrong, now correct
7 years ago
f8b5dc97eb
update SD card power supply and gerbers
7 years ago
bab7ee607e
placeholder for 1.5k pullup for usb 1.0
7 years ago
9cc436ce8c
Additional VCC 2.2uF blocking capacitors near the switching
...
power supply to form PI-filter with another 2.2uF near BGA
7 years ago
f120d212d9
433 MHz onboard antenna (need to uncover copper infill layers)
7 years ago
0229a768ad
FPGA direct-to-pin Hackish USB transciver 27 ohm + 3.6 V zener
7 years ago
fdf38ad9a1
DIP switch moved to the right, near RAM.
...
Maybe should be moved more to the right not to overlap with OLED
7 years ago
236f63488a
DIP SWITCH routed
7 years ago
6d14ed8ff0
Placing DIP switch, but not yet connecting it to FPGA
7 years ago
37bb008e24
ADC connecting REF+/REF- and SPI
7 years ago
2153a220a0
schematic symbol for ADC MAX11123
...
small PCB traces cleanup
ADC chip placed on PCB but connected only to GND
7 years ago
be09416928
Add 27 ohm resistors in series with FTDI USB and readme update
8 years ago
81b3ea5da0
adding minimal set of 3 2.2uF capacitor for 1.2V, 2.5V and 3.3V
8 years ago
ee7d266543
Resistors for LEDs
8 years ago
18aef04f2c
JTAG header
8 years ago
238ad770ce
moving USB LEDs on TOP layer
8 years ago
b7500cc477
increasing thickness of power traces, moving clock
...
to a bank which is always at 3.3V
8 years ago
23b588ff16
Routing... 4 routes remaining
8 years ago
0f9d00f602
Buffer capacitor for SDRAM
8 years ago
1e5e0b01a6
connecting JTAG lines to FTDI serial lines RI DCD CTS DSR
...
as those pins are by default inputs and can be reconfigured as outputs
similar but not identical pinout as the one that works from ujprog
CBUS used to force-wakeup of the board from sleep state
2 LEDs to CBUS pins to display usb enumeration and activity status
8 years ago
feb31c8f87
moving inner layer routes away from BGA
8 years ago
dcc2d375ea
routing additional pins to J2 GPIO. 2 differential pairs left to route
8 years ago
9f0d9c46a7
routing half of J2 gpio
8 years ago
e30bbeea40
routing 4 GPIO on J2
8 years ago
19b884baef
using corrected schem symbol, reordering pins
8 years ago
39dce76f0a
use new schem symbol
8 years ago
70fb21781b
reorder GPDI differential pairs for almost straitforward routing
8 years ago
a8f1214b27
reorder SDRAM to FPGA connection for straightforward routing
8 years ago
davor