1121 Commits (5024b15242019edb66342b999305ef96d1784a0a)
 

Author SHA1 Message Date
davor aa5d542fd8 shrinking the board
8 years ago
davor 0f20405afd chip name edited on JTAG to be the same as all units
8 years ago
davor aa1e65bd71 small edits
8 years ago
davor 1b53425bb2 changing chip name and slightly reordering blocks in the schematics
8 years ago
davor f6326e22d9 changing BANK0 (Unit A) shematic symbol and
8 years ago
Davor dbc2694b65 2 holes set correct layer "Edge cuts"
8 years ago
Davor 25672b71ff updating pins for BANK1 (still incomplete)
8 years ago
Davor 7b52ca0707 reverting layout back to original, just a bit larger board
8 years ago
Davor fbc265154d FPGA aligned to 0.2 mm raster and one trace routead as example
8 years ago
Davor fdfb12770c add missing library footprint/usb_otg
8 years ago
Davor cf484ec2ff screw holes proper spacing for M3
8 years ago
Marko Zec 400daf5642 Reduce board size to 92.5 x 49.3 mm, reshuffle components.
8 years ago
davor 721a1de0d2 readme update
8 years ago
davor ad04bf4309 Readme update for new board size
8 years ago
davor 1ea9bbff9e correct spacing of the screw holes
8 years ago
davor 9afb686693 using connectors 2x32 for general purpose and 2x15 for 2 PMODs
8 years ago
Davor 3a34e66ca9 2x40 pin connector
8 years ago
Davor c52fe53c1e Departing from RPI-0 size to a 56x106 mm board
8 years ago
davor 9435038a8b readme todo updated
9 years ago
davor 3f8b5009a9 Uploading initial kicad project for ULX3S
9 years ago
davor de89769629 first commit
9 years ago