Emard
|
5432fd6540
|
connecting clock and ftdi USB
|
7 years ago |
|
Emard
|
4c13f262e8
|
connecting FTDI TXD/RXD
|
7 years ago |
|
Emard
|
092e601af1
|
connecting LEDs
|
7 years ago |
|
Emard
|
364957f9e0
|
connecting OLED
|
7 years ago |
|
Emard
|
feb31c8f87
|
moving inner layer routes away from BGA
|
7 years ago |
|
Emard
|
24c52062fa
|
moving routes under BGA out of inner layers
|
7 years ago |
|
Emard
|
6e2e5f8c39
|
moving routing out of inner layers under BGA to allow
larger copper fill zone for power supply
|
7 years ago |
|
davor
|
3a9160cb16
|
scrapping current routing, placing power supply on copper zones under the BGA
|
7 years ago |
|
davor
|
21aa552e1a
|
placing copper fill zones for power supply by the book
similar to TN1074
|
7 years ago |
|
Emard
|
37f7a62a25
|
reducing minimal drill size to 0.2 mm as
recommended in lattice BGA guide.
Seeedstudio meets this capabilities
OSHpark doesn't
|
7 years ago |
|
Emard
|
1392c5aa2b
|
how to route BGA
|
7 years ago |
|
Emard
|
8061b47da8
|
moving some resistor near flash chip
|
7 years ago |
|
Emard
|
b12f1b64a6
|
routing spi flash lines
|
7 years ago |
|
Emard
|
820f30f598
|
routing JTAG
|
7 years ago |
|
davor
|
3a079bd1d2
|
moving some resistor closer to ftdi
|
7 years ago |
|
davor
|
48f79d581b
|
reordering PCB elements to simplify or shorten routes
|
7 years ago |
|
Emard
|
6e48d42150
|
fully routed GPIO
|
7 years ago |
|
davor
|
dcc2d375ea
|
routing additional pins to J2 GPIO. 2 differential pairs left to route
|
7 years ago |
|
davor
|
9f0d9c46a7
|
routing half of J2 gpio
|
7 years ago |
|
Emard
|
e30bbeea40
|
routing 4 GPIO on J2
|
7 years ago |
|
Emard
|
48dc148919
|
manually routing J1 differential
|
7 years ago |
|
Emard
|
9050eefd6e
|
update fill zone
|
7 years ago |
|
Davor
|
55ecd6c1c2
|
update 3D view top
|
7 years ago |
|
Davor
|
56e8ad2710
|
update 3D view pictures
|
7 years ago |
|
Davor
|
3446afcc08
|
optimizing PCB component placement
and audio bit ordering
|
7 years ago |
|
Davor
|
19b884baef
|
using corrected schem symbol, reordering pins
|
7 years ago |
|
Davor
|
a4b74230d3
|
fixing errors in schem symbol BANK6
|
7 years ago |
|
Davor
|
af58a36fbd
|
delete old FPGA schem. symbol component from the library
|
7 years ago |
|
Davor
|
39dce76f0a
|
use new schem symbol
|
7 years ago |
|
Davor
|
e5f97e1897
|
schematic symbol FPGA: mark bank physical location
on the floorplan
|
7 years ago |
|
Davor
|
2cda80c3a8
|
manually routed few tracks of GPIO
|
7 years ago |
|
Davor
|
8a53acb71a
|
cleaning GPDI routes and moving OLED back in place
|
7 years ago |
|
davor
|
70fb21781b
|
reorder GPDI differential pairs for almost straitforward routing
|
7 years ago |
|
davor
|
4a26254f9a
|
correcting schematic symbol of FPGA
|
7 years ago |
|
davor
|
a8f1214b27
|
reorder SDRAM to FPGA connection for straightforward routing
|
7 years ago |
|
davor
|
01d1cad2ec
|
add missing pins in schematic symbol for BANK3
|
7 years ago |
|
Davor
|
19c91e5c6b
|
differential pair track thickness and spacing
|
7 years ago |
|
Davor
|
632e5bd443
|
importing netlist with differential pairs named + -
|
7 years ago |
|
Davor
|
aef3945a8e
|
differential pin naming for GPDI, USB, GPIO
|
7 years ago |
|
Davor
|
d0791b1e47
|
correcting few pin numbering errors in FPGA schematic symbols
|
7 years ago |
|
Davor
|
ec42a18d26
|
reordering RAM connections to use peripheral pins near SDRAM chip
|
7 years ago |
|
Davor
|
40aef19979
|
FPGA schematic symbol add mssing PR41A, PR41B to BANK3
|
7 years ago |
|
davor
|
53f11a6950
|
reducing track width to 0.19 mm to pass out of 2nd row of BGA
|
7 years ago |
|
Davor
|
961755fc98
|
manual routing BGA power
|
7 years ago |
|
Davor
|
af042dfef0
|
manually routing BGA power
|
7 years ago |
|
davor
|
a1d25d9d24
|
create copper fill layers
|
7 years ago |
|
davor
|
d6fd30e59c
|
jumper to disable wifi module
|
7 years ago |
|
davor
|
38517df9f6
|
fine tuning via diameters and clearances
|
7 years ago |
|
davor
|
dd597e7b49
|
board production rules for oshpart
|
7 years ago |
|
davor
|
1c5b8a64a3
|
use new footprint for crystal oscillator
|
7 years ago |
