correctly now, either because SPI is in 16-bit mode, or because I found
all the other bugs!
Doubled SPI baudrate to 10.5Mbps. Transfer speed now limited (again) by
Downstream's lack of FIFO buffering in the USB host controller.
Also disabled DMA transaction half-complete interrupt in
stm32f4xx_hal_dma.c, as it wasn't doing anything useful.
NOTE: Downstream's full-speed host controller is flakey when connecting
to low-speed devices. One mouse enumerates on only 50% of connection
events, while another mouse enumerates on 90% of connections. Grrr.
SPI peripheral library. At this speed SPI requires ~60% CPU time at -Og
optimisation level. This could be further improved by trimming down the
SPI interrupt. But...
Speed is now limited by Downstream's single-packet-per-URB restriction,
to about 460kB/s. USB Middleware does not implement TX FIFO empty
interrupt, so a bit of work is required here.
Although I am not entirely convinced this is necessary, as the SPI data
stall issue only appeared with optimisation off (-O0). Perhaps re-visit
this if Upstream needs more free CPU time later...
interacts with SPI.
It elevates to USB_OTG priority to avoid preemption by SPI, DMA, or USB
interrupts thus avoiding synchronisation issues between USB host stack
and SPI interface.
Also minor improvements to Downstream error handling.
Robert Fisk