Previously we wrote 4 x 64 byte transactions to the downstream device.
This is fast, but very occasionally the USB host silicon would bug out.
Reverting to single 64 byte write transactions increases reliability at
the expense of some write speed.
It will sometimes NAK part-way through a multi-packet OUT URB. And what
it wants is for the host to resend beginning from the last even-numbered
packet. NOT the last packet it received, and NOT the beginning of that
URB.
It turned out we were getting a "device disconnected" interrupt while
waiting for the port to enable following reset. Simply ignoring the
disconnect interrupt allows everything to work! WTF...
Each USB transaction passed to the driver now consists of multiple
64-byte packets. 8 packets when receiving, 4 packets when transmitting.
The STM32 silicon bugs out when more than 4 packets are scheduled to
write at a time :(
Reads 1.0MB/sec, writes 967kB/sec, not CPU limited :)
- Unexpected second port-connected interrupt on cold boot with low-speed
device connected.
- Retry on failure to get device descriptor. (We still fail after three
attempts, but that is better than failing after the first one!)
Also changed eclipse project to use external builder.
some flash drives can take up to 2 seconds to write a single block.
Also, reverting the previous two commits because they didn't actually
help. Aughhhhhh...
So there's a host controller hardware bug on the STM32F407 that
manifests when writing to some FAT filesystems. Transactions will stop
partway through a 512-byte write, and nothing can get them started
again. We can avoid this by soft-resetting the AHB-interface state
machines on every channel halt.
correctly now, either because SPI is in 16-bit mode, or because I found
all the other bugs!
Doubled SPI baudrate to 10.5Mbps. Transfer speed now limited (again) by
Downstream's lack of FIFO buffering in the USB host controller.
Also disabled DMA transaction half-complete interrupt in
stm32f4xx_hal_dma.c, as it wasn't doing anything useful.
SPI peripheral library. At this speed SPI requires ~60% CPU time at -Og
optimisation level. This could be further improved by trimming down the
SPI interrupt. But...
Speed is now limited by Downstream's single-packet-per-URB restriction,
to about 460kB/s. USB Middleware does not implement TX FIFO empty
interrupt, so a bit of work is required here.
Robert Fisk