Added timeout checks and retry functionality to control transaction
state machine. But some times the device just won't talk, so we flash
the fault LED slowly to give the user some clue about what happened.
- Unexpected second port-connected interrupt on cold boot with low-speed
device connected.
- Retry on failure to get device descriptor. (We still fail after three
attempts, but that is better than failing after the first one!)
Also changed eclipse project to use external builder.
Our custom OpenOCD scripts are now linked directly into the Eclipse debug configurations.
No need to manually copy the files into OpenOCD's script directory.
Our custom OpenOCD scripts are now linked directly into the Eclipse
debug configurations. No need to manually copy the files into OpenOCD's
script directory.
some flash drives can take up to 2 seconds to write a single block.
Also, reverting the previous two commits because they didn't actually
help. Aughhhhhh...
So there's a host controller hardware bug on the STM32F407 that
manifests when writing to some FAT filesystems. Transactions will stop
partway through a 512-byte write, and nothing can get them started
again. We can avoid this by soft-resetting the AHB-interface state
machines on every channel halt.
some circumstances the 405 is equally buggy as the 401!
Work around an intermittent stall/timeout by busy-waiting Upstream's
packet length transmission and reception, instead of DMA-ing it like the
packet body. Ugh...
correctly now, either because SPI is in 16-bit mode, or because I found
all the other bugs!
Doubled SPI baudrate to 10.5Mbps. Transfer speed now limited (again) by
Downstream's lack of FIFO buffering in the USB host controller.
Also disabled DMA transaction half-complete interrupt in
stm32f4xx_hal_dma.c, as it wasn't doing anything useful.
NOTE: Downstream's full-speed host controller is flakey when connecting
to low-speed devices. One mouse enumerates on only 50% of connection
events, while another mouse enumerates on 90% of connections. Grrr.
SPI peripheral library. At this speed SPI requires ~60% CPU time at -Og
optimisation level. This could be further improved by trimming down the
SPI interrupt. But...
Speed is now limited by Downstream's single-packet-per-URB restriction,
to about 460kB/s. USB Middleware does not implement TX FIFO empty
interrupt, so a bit of work is required here.
Although I am not entirely convinced this is necessary, as the SPI data
stall issue only appeared with optimisation off (-O0). Perhaps re-visit
this if Upstream needs more free CPU time later...
Robert Fisk