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i2c update

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master
Ivan Olenichev 6 years ago
parent df40598fbc
commit a6ceebc5ce
15 changed files with 32905 additions and 28467 deletions
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i2c_keyboard/.sconsign.dblite
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i2c_keyboard/descriptors.v
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@ -1,4 +1,4 @@
module descriptors (input CLK, input RESET, input RD_REQUEST, input [1:0] DESC_TYPE, input [7:0] ADR, output reg [7:0] VAL/*, input [63:0] kbd_report*/); module descriptors (input CLK, input RESET, input RD_REQUEST, input [1:0] DESC_TYPE, input [7:0] ADR, output /*reg*/ [7:0] VAL/*, input [63:0] kbd_report*/);
parameter HID_REPORT_DESC_LEN = 63; parameter HID_REPORT_DESC_LEN = 63;
//reg [(8*30-1):0] i2c_hid_desc;// = 'h_1E_00__00_01__46_00__02_00__03_00__0A_00__04_00__03_00__05_00__06_00__9F_04__01_01__00_01__00_00_00_00; //reg [(8*30-1):0] i2c_hid_desc;// = 'h_1E_00__00_01__46_00__02_00__03_00__0A_00__04_00__03_00__05_00__06_00__9F_04__01_01__00_01__00_00_00_00;
@ -7,6 +7,10 @@ parameter HID_REPORT_DESC_LEN = 63;
parameter READ_ADRESS_OFFSET = 2; parameter READ_ADRESS_OFFSET = 2;
reg last_rd_request = 0; reg last_rd_request = 0;
reg tx_flag = 0; // AT POSEDGE OF RD_REQUEST DATA FROM RAM MOVES TO RAM_RD_REG, AT NEXT CLK DATA MUST BE WRITE TO VAL
reg [7:0] real_adress;
//reg [7:0] ram_rd_t1;
//reg [7:0] ram_rd_t2;
always @ (posedge CLK) begin always @ (posedge CLK) begin
if (RESET == 0) begin if (RESET == 0) begin
@ -15,11 +19,24 @@ always @ (posedge CLK) begin
//i2c_hid_desc [207:200] <= HID_REPORT_DESC_LEN[7:0]; //i2c_hid_desc [207:200] <= HID_REPORT_DESC_LEN[7:0];
//i2c_hid_desc [199:192] <= HID_REPORT_DESC_LEN[15:8]; //i2c_hid_desc [199:192] <= HID_REPORT_DESC_LEN[15:8];
last_rd_request <= 0; last_rd_request <= 0;
real_adress = 0;
end end
else begin else begin
/*if (tx_flag == 1) begin // NEXT CLK AFTER POSEDGE REQUEST
if (DESC_TYPE == 1)
VAL <= ram_rd_t1;
else
VAL <= ram_rd_t2;
tx_flag = 0;*/
//end
if ((last_rd_request == 0) && (RD_REQUEST == 1)) begin if ((last_rd_request == 0) && (RD_REQUEST == 1)) begin
if (DESC_TYPE == 1) begin if (DESC_TYPE == 1)
case (ADR) 2: VAL <= 8'h1E; 3: VAL <= 0; // 2-3 - DESCR LEN (30), real_adress = ADR;
else
real_adress = ADR + 32;
//if (DESC_TYPE == 1) begin
tx_flag = 1; // WAIT NEXT CLK
/* case (ADR) 2: VAL <= 8'h1E; 3: VAL <= 0; // 2-3 - DESCR LEN (30),
4: VAL <= 0; 5: VAL <= 1; // 4-5 - bcdVersion 4: VAL <= 0; 5: VAL <= 1; // 4-5 - bcdVersion
6: VAL <= HID_REPORT_DESC_LEN[7:0]; 7: VAL <= HID_REPORT_DESC_LEN[15:8]; 6: VAL <= HID_REPORT_DESC_LEN[7:0]; 7: VAL <= HID_REPORT_DESC_LEN[15:8];
8: VAL <= 2; 9: VAL <= 0; // 8-9 - REPORT DESC ADR 8: VAL <= 2; 9: VAL <= 0; // 8-9 - REPORT DESC ADR
@ -34,8 +51,9 @@ always @ (posedge CLK) begin
26: VAL <= 0; 27: VAL <= 1; // 26-27 - VERSION 26: VAL <= 0; 27: VAL <= 1; // 26-27 - VERSION
28: VAL <= 0; 29: VAL <= 0; 30: VAL <= 0; 31: VAL <= 0; // 28-31 - RSVD 28: VAL <= 0; 29: VAL <= 0; 30: VAL <= 0; 31: VAL <= 0; // 28-31 - RSVD
default: VAL <= 0; default: VAL <= 0;
endcase endcase*/
end
/*end
else if (DESC_TYPE == 2) begin else if (DESC_TYPE == 2) begin
case (ADR) 2: VAL <= 8'h05; 3: VAL <= 8'h01; case (ADR) 2: VAL <= 8'h05; 3: VAL <= 8'h01;
4: VAL <= 8'h09; 5: VAL <= 8'h06; 4: VAL <= 8'h09; 5: VAL <= 8'h06;
@ -78,7 +96,7 @@ always @ (posedge CLK) begin
64: VAL <= 8'hC0; 64: VAL <= 8'hC0;
default: VAL <= 0; default: VAL <= 0;
endcase endcase
end end*/
/*if (READ_TYPE == 1) begin /*if (READ_TYPE == 1) begin
if ((READ_ADRESS < READ_ADRESS_OFFSET) || (READ_ADRESS > (READ_ADRESS_OFFSET + 30 - 1))) if ((READ_ADRESS < READ_ADRESS_OFFSET) || (READ_ADRESS > (READ_ADRESS_OFFSET + 30 - 1)))
VAL <= 0; VAL <= 0;
@ -106,6 +124,84 @@ always @ (posedge CLK) begin
end end
end end
/* 2: VAL <= 8'h1E; 3: VAL <= 0; // 2-3 - DESCR LEN (30),
4: VAL <= 0; 5: VAL <= 1; // 4-5 - bcdVersion
6: VAL <= HID_REPORT_DESC_LEN[7:0]; 7: VAL <= HID_REPORT_DESC_LEN[15:8];
8: VAL <= 2; 9: VAL <= 0; // 8-9 - REPORT DESC ADR
10: VAL <= 3; 11: VAL <= 0; // 10-11 - INPUT REG ADR
12: VAL <= 10; 13: VAL <= 0; // 12-13 - INPUT REG LEN
14: VAL <= 4; 15: VAL <= 0; // 14-15 - OUT REG ADR
16: VAL <= 3; 17: VAL <= 0; // 16-17 - OUT REG LEN
18: VAL <= 5; 19: VAL <= 0; // 18-19 - CMD REG ADR
20: VAL <= 6; 21: VAL <= 0; // 20-21 - DATA REG ADR
22: VAL <= 8'h9F; 23: VAL <= 4; // 22-23 - VENDOR ID
24: VAL <= 1; 25: VAL <= 1; // 24-25 - DEVICE ID
26: VAL <= 0; 27: VAL <= 1; // 26-27 - VERSION
28: VAL <= 0; 29: VAL <= 0; 30: VAL <= 0; 31: VAL <= 0; // 28-31 - RSVD
*/
SB_RAM40_4K #(
.INIT_0(256'h0000_0004__0000_000A__0000_0003__0000_0002__0000_003F__0001_0000__0000_001E___0000_0000),
.INIT_1(256'h0000_0000__0000_0000__0001_0000__0001_0001__0004_009F__0000_0006__0000_0005___0000_0003),
.INIT_2(256'h0000_0015__00E7_0029__00E0_0019__0007_0005__0001_00A1__0006_0009__0001_0005___0000_0000),
.INIT_3(256'h0005_0095__0001_0081__0008_0075__0001_0095__0002_0081__0008_0095__0001_0075___0001_0025),
.INIT_4(256'h0003_0091__0003_0075__0001_0095__0002_0091__0005_0029__0001_0019__0008_0005___0001_0075),
.INIT_5(256'h0000_0081__0065_0029__0000_0019__0007_0005__0065_0025__0000_0015__0008_0075___0006_0095),
.INIT_6(256'h0000_0000__0000_0000__0000_0000__0000_0000__0000_0000__0000_0000__0000_0000___0000_00C0),
.WRITE_MODE(1),
.READ_MODE(1)
) descriptors (
.RDATA(VAL),
.RADDR(real_adress),
.RCLK(CLK),
.RCLKE(1'b1),
.RE(1'b1),
.WADDR(8'b0),
.WCLK(1'b0),
.WCLKE(1'b0),
.WDATA(8'b0),
.WE(1'b0)
);
/*
SB_RAM40_4K #(
.INIT_0(256'h0000_0004__0000_000A__0000_0003__0000_0002__0000_003F__0001_0000__0000_001E___0000_0000),
.INIT_1(256'h0000_0000__0000_0000__0001_0000__0001_0001__0004_009F__0000_0006__0000_0005___0000_0003),
.WRITE_MODE(1),
.READ_MODE(1)
) i2c_hid_desc (
.RDATA(ram_rd_t1),
.RADDR(ADR),
.RCLK(CLK),
.RCLKE(1'b1),
.RE(1'b1),
.WADDR(8'b0),
.WCLK(1'b0),
.WCLKE(1'b0),
.WDATA(8'b0),
.WE(1'b0)
);
SB_RAM40_4K #(
.INIT_0(256'h0000_0015__00E7_0029__00E0_0019__0007_0005__0001_00A1__0006_0009__0001_0005___0000_0000),
.INIT_1(256'h0005_0095__0001_0081__0008_0075__0001_0095__0002_0081__0008_0095__0001_0075___0001_0025),
.INIT_2(256'h0003_0091__0003_0075__0001_0095__0002_0091__0005_0029__0001_0019__0008_0005___0001_0075),
.INIT_3(256'h0000_0081__0065_0029__0000_0019__0007_0005__0065_0025__0000_0015__0008_0075___0006_0095),
.INIT_4(256'h0000_0000__0000_0000__0000_0000__0000_0000__0000_0000__0000_0000__0000_0000___0000_00C0),
.WRITE_MODE(1),
.READ_MODE(1)
) hid_report_desc (
.RDATA(ram_rd_t2),
.RADDR(ADR),
.RCLK(CLK),
.RCLKE(1'b1),
.RE(1'b1),
.WADDR(8'b0),
.WCLK(1'b0),
.WCLKE(1'b0),
.WDATA(8'b0),
.WE(1'b0)
);*/
endmodule endmodule
//static const uint8 hid_descriptor_keyboard[] = { //static const uint8 hid_descriptor_keyboard[] = {

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i2c_keyboard/hardware.asc
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i2c_keyboard/hardware.bin
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i2c_keyboard/hardware.blif
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i2c_keyboard/i2c_kbd_alt.bin
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i2c_keyboard/i2c_kbd_alt.blif
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i2c_keyboard/i2c_kbd_alt.ex
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i2c_keyboard/i2c_kbd_alt.txt
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i2c_keyboard/i2c_slave.v
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@ -13,7 +13,8 @@ module i2c_slave (input CLK, input RESET,
parameter I2C_ADRESS = 7'h34; parameter I2C_ADRESS = 7'h34;
parameter MAX_I2C_TRANSACTION_EXP2 = 8; // !!! - FOR LIMIT BYTES TO TX/RX (WITH ADRESS) parameter MAX_I2C_TRANSACTION_EXP2 = 8; // !!! - FOR LIMIT BYTES TO TX/RX (WITH ADRESS)
reg SDA_IN, SDA_DIR, SDA_OUT; reg /*SDA_IN,*/ SDA_DIR, SDA_OUT;
wire SDA_IN;
initial begin initial begin
SDA_OUT = 0; SDA_OUT = 0;
end end

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i2c_keyboard/inouts.pcf
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@ -19,15 +19,38 @@ set_io INTERRUPT 88 # J2, 8
# GND - J2, 11 # GND - J2, 11
#set_io INT 95 #set_io INT 95
set_io KBD_COLUMNS[0] 78 #J2-1 or PIO1-02 #set_io KBD_COLUMNS[0] 78 #J2-1 or PIO1-02
set_io KBD_COLUMNS[1] 79 #J2-2 or PIO1-03 #set_io KBD_COLUMNS[1] 79 #J2-2 or PIO1-03
set_io KBD_COLUMNS[2] 80 #J2-3 or PIO1-04 #set_io KBD_COLUMNS[2] 80 #J2-3 or PIO1-04
set_io KBD_COLUMNS[3] 81 #J2-4 or PIO1-05 #set_io KBD_COLUMNS[3] 81 #J2-4 or PIO1-05
set_io KBD_COLUMNS[0] 44 #J3-10 or PIO2-10
set_io KBD_COLUMNS[1] 45 #J3-9 or PIO2-11
set_io KBD_COLUMNS[2] 47 #J3-8 or PIO2-12
set_io KBD_COLUMNS[3] 48 #J3-7 or PIO2-13
set_io KBD_COLUMNS[4] 56 #J3-6 or PIO2-14
set_io KBD_COLUMNS[5] 60 #J3-5 or PIO2-15
set_io KBD_COLUMNS[6] 61 #J3-4 or PIO2-16
set_io KBD_COLUMNS[7] 62 #J3-3 or PIO2-17
set_io KBD_ROWS[0] 119 #J1-10 or PIO0-09 set_io KBD_ROWS[0] 119 #J1-10 or PIO0-09
set_io KBD_ROWS[1] 118 #J1-9 or PIO0-08 set_io KBD_ROWS[1] 118 #J1-9 or PIO0-08
set_io KBD_ROWS[2] 117 #J1-8 or PIO0-07 set_io KBD_ROWS[2] 117 #J1-8 or PIO0-07
set_io KBD_ROWS[3] 116 #J1-7 or PIO0-06 set_io KBD_ROWS[3] 116 #J1-7 or PIO0-06
set_io KBD_ROWS[4] 115 #J1-6 or PIO0-05
set_io KBD_ROWS[5] 114 #J1-5 or PIO0-04
set_io KBD_ROWS[6] 113 #J1-4 or PIO0-03
set_io KBD_ROWS[7] 112 #J1-3 or PIO0-02
set_io KBD_ROWS[8] 78 #J2-1 or PIO1-02
set_io KBD_ROWS[9] 79 #J2-2 or PIO1-03
set_io KBD_ROWS[10] 80 #J2-3 or PIO1-04
set_io KBD_ROWS[11] 81 #J2-4 or PIO1-05
set_io KBD_ROWS[12] 87 #J2-7 or PIO1-06
set_io KBD_ROWS[13] 37 #PIO2-04
set_io KBD_ROWS[14] 38 #PIO2-05
set_io KBD_ROWS[15] 39 #PIO2-06
set_io COM_TX 8 set_io COM_TX 8
set_io COM_RX 9 set_io COM_RX 9

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i2c_keyboard/matrix_kbd.v
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@ -1,4 +1,4 @@
module matrix_kbd (input CLK, input RESET, input FREEZE, inout [3:0] ROWS, input [3:0] COLUMNS, output [63:0] kbd_report, output INT); module matrix_kbd (input CLK, input RESET, input FREEZE, inout [15:0] ROWS, input [7:0] COLUMNS, output [7:0] kbd_r0, kbd_r2, kbd_r3, kbd_r4, kbd_r5, kbd_r6, kbd_r7, output INT);
// * - ESC (29), 7 - F1 (3A), 4 - F2 (3B), 1 - NUM_LOCK (53) // * - ESC (29), 7 - F1 (3A), 4 - F2 (3B), 1 - NUM_LOCK (53)
// 0 - CAPS LOCK (39), 8 - R (15), 5 - BACKSPACE (2A), 2 - ENTER (58) // 0 - CAPS LOCK (39), 8 - R (15), 5 - BACKSPACE (2A), 2 - ENTER (58)
@ -6,180 +6,188 @@ module matrix_kbd (input CLK, input RESET, input FREEZE, inout [3:0] ROWS, input
// D - LCTRL (E0), C - LALT (E2), B - SPACE (2C), A - RGUI (E7) // D - LCTRL (E0), C - LALT (E2), B - SPACE (2C), A - RGUI (E7)
parameter ONE_ROW_TIME = 12000; parameter ONE_ROW_TIME = 12000;
parameter ROW_STT_PROCESS_TIME = 11000;
parameter ONE_COLUMN_PROCESS_TIME = 50;
reg [15:0] row_time = 0; reg [15:0] row_time = 0;
reg [1:0] row_counter; reg [3:0] row_counter;
reg [15:0] last_data; reg [7:0] temp;
reg [7:0] i; reg [7:0] i;
reg [63:0] report; reg [7:0] report [6:0]; // NO BYTE 2
reg [5:0] report_free_place;
reg isr; reg isr;
reg [3:0] ROWS_EN = 0; reg [15:0] ROWS_EN = 0;
reg [3:0] ROWS_OUT = 0; reg [15:0] ROWS_OUT = 0;
wire [3:0] ROWS_IN; wire [15:0] ROWS_IN;
reg [3:0] COLS_SHADOW; reg [7:0] COLS_SHADOW;
reg [7:0] kbd_code; reg [7:0] kbd_code;
wire [7:0] kbd_code_hid;
reg is_pressed; reg is_pressed;
reg ram_wr;
reg [8:0] ram_adr;
wire [7:0] ram_rd;
reg [8:0] init_ram_cnt;
always @ (negedge CLK) begin always @ (negedge CLK) begin
COLS_SHADOW <= COLUMNS; COLS_SHADOW <= COLUMNS;
end end
ram RAM (CLK, ram_wr, ram_adr, temp, ram_adr, ram_rd);//module ram(input clk, wen, input [8:0] addr, input [7:0] wdata, output [7:0] rdata);
always @ (posedge CLK) begin always @ (posedge CLK) begin
if (RESET == 0) begin if (RESET == 0) begin
last_data <= 16'hFFFF; for (i = 0; i < 6; i = i + 1)
report_free_place <= 6'h3F; report[i] = 0;
report <= 63'h_00_00_00_00_00_00_00_00; isr = 0;
init_ram_cnt = 0;
end end
else begin else begin
if (FREEZE == 0) begin if (FREEZE == 0) begin
if (init_ram_cnt < 256) begin
ram_wr = 1;
ram_adr = init_ram_cnt;
temp = 255;
init_ram_cnt = init_ram_cnt + 1;
end
else if (init_ram_cnt == 256) begin
ram_wr = 0;
init_ram_cnt = init_ram_cnt + 1;
end
else begin
if (row_time == ONE_ROW_TIME) begin if (row_time == ONE_ROW_TIME) begin
ram_wr = 0;
row_time <= 0; row_time <= 0;
row_counter = row_counter + 1; row_counter = row_counter + 1;
ROWS_EN = 1 << row_counter; ROWS_EN = 1 << row_counter;
ram_adr = row_counter;
end end
else else
row_time <= row_time + 1; row_time <= row_time + 1;
// ROW 0 - D, 1 - A, 2 - C, 3 - B // ROW 0 - D, 1 - A, 2 - C, 3 - B
if (row_time == (ONE_ROW_TIME/2 + 0)) begin if (row_time == (ROW_STT_PROCESS_TIME - 1))
if (COLS_SHADOW[0] != last_data[row_counter*4 + 0]) begin temp = ram_rd;
case (row_counter) 0: kbd_code = 8'h29; 1: kbd_code = 8'h53; 2: kbd_code = 8'h3A; 3: kbd_code = 8'h3B; // ESC, F1-F2, NUM LOCK if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 7 + 1))
default: kbd_code = 1; ram_wr = 1;
endcase if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 0))
if ((COLS_SHADOW[0] == 0) && (last_data[row_counter*4 + 0] == 1)) is_pressed = 1; check_column (0);
else is_pressed = 0; else if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 2))
end check_column (2);
else kbd_code = 0; else if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 1))
last_data[row_counter*4 + 0] <= COLS_SHADOW[0]; check_column (1);
end else if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 3))
check_column (3);
else if (row_time == (ONE_ROW_TIME/2 + 4)) begin else if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 4))
if (COLS_SHADOW[2] != last_data[row_counter*4 + 2]) begin check_column (4);
case (row_counter) 0: kbd_code = 8'h39; 1: kbd_code = 8'h58; 2: kbd_code = 8'h15; 3: kbd_code = 8'h2A; // CAPS LOCK, R, BACKSPACE, ENTER else if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 5))
default: kbd_code = 1; check_column (5);
endcase else if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 6))
if ((COLS_SHADOW[2] == 0) && (last_data[row_counter*4 + 2] == 1)) is_pressed = 1; check_column (6);
else is_pressed = 0; else if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 7))
end check_column (7);
else kbd_code = 0;
last_data[row_counter*4 + 2] <= COLS_SHADOW[2];
end
else if (row_time == (ONE_ROW_TIME/2 + 2)) begin
if (COLS_SHADOW[1] != last_data[row_counter*4 + 1]) begin
case (row_counter) 0: kbd_code = 8'hE1; 1: kbd_code = 8'h4C; 2: kbd_code = 8'h06; 3: kbd_code = 8'h19; // LEFT SHIFT, C, V, DELETE
default: kbd_code = 1;
endcase
if ((COLS_SHADOW[1] == 0) && (last_data[row_counter*4 + 1] == 1)) is_pressed = 1;
else is_pressed = 0;
end
else kbd_code = 0;
last_data[row_counter*4 + 1] <= COLS_SHADOW[1];
end
else if (row_time == (ONE_ROW_TIME/2 + 6)) begin
if (COLS_SHADOW[3] != last_data[row_counter*4 + 3]) begin
case (row_counter) 0: kbd_code = 8'hE0; 1: kbd_code = 8'hE7; 2: kbd_code = 8'hE2; 3: kbd_code = 8'h2C; // LCTRL, LALT, SPACE, RGUI
default: kbd_code = 1;
endcase
if ((COLS_SHADOW[3] == 0) && (last_data[row_counter*4 + 3] == 1)) is_pressed = 1;
else is_pressed = 0;
end
else kbd_code = 0;
last_data[row_counter*4 + 3] <= COLS_SHADOW[3];
end
else else
kbd_code = 0; kbd_code = 255;
// START PACK I2C_HID REPORT // START PACK I2C_HID REPORT
if (kbd_code != 0) begin if (kbd_code_hid != 0) begin
isr = 1; if ((kbd_code_hid > 8'hDF) && (kbd_code_hid < 8'hE8)) begin
report[15:8] <= 0;
//report[63:56] <= 0;
if ((kbd_code > 8'hDF) && (kbd_code < 8'hE8)) begin
kbd_code = kbd_code & 8'h07;
if (is_pressed) if (is_pressed)
report [7:0] <= report [7:0] | (1<<kbd_code); report [0] = report [0] | (1<<(kbd_code_hid & 8'h07));
else else
report [7:0] <= report [7:0] & (~(1<<kbd_code)); report [0] <= report [0] & (~(1<<(kbd_code_hid & 8'h07)));
end end
else begin else begin
if (is_pressed) begin if (is_pressed) begin
/*for (i = 0; i < 4; i = i + 1) begin isr = 1;
if (report_free_place[i] == 1) begin if (report [ 1 ] == 0)
report [ ((i + 2) * 8 + 7) : ((i + 2) * 8 + 0)] <= kbd_code; report [ 1 ] <= kbd_code_hid;
report_free_place[i] = 0; else if (report [ 2 ] == 0)
is_pressed = 0; // NO ERROR DETECTED report [ 2 ] <= kbd_code_hid;
end else if (report [ 3 ] == 0)
end report [ 3 ] <= kbd_code_hid;
if (report_free_place[0] == 1) begin else if (report [ 4 ] == 0)
report [ ((0 + 2) * 8 + 7) : ((0 + 2) * 8 + 0)] <= kbd_code; report [ 4 ] <= kbd_code_hid;
report_free_place[0] = 0; else if (report [ 5 ] == 0)
end*/ report [ 5 ] <= kbd_code_hid;
if (report [ 23 : 16 ] == 0) else if (report [ 6 ] == 0)
report [ 23 : 16 ] <= kbd_code; report [ 6 ] <= kbd_code_hid;
else if (report [ 31 : 24 ] == 0) else
report [ 31 : 24 ] <= kbd_code; isr = 0;
else if (report [ 39 : 32 ] == 0)
report [ 39 : 32 ] <= kbd_code;
else if (report [ 47 : 40 ] == 0)
report [ 47 : 40 ] <= kbd_code;
else if (report [ 55 : 48 ] == 0)
report [ 55 : 48 ] <= kbd_code;
else if (report [ 63 : 56 ] == 0)
report [ 63 : 56 ] <= kbd_code;
end end
else begin else begin
for (i = 0; i < 6; i = i + 1) begin for (i = 1; i < 7; i = i + 1) begin
if (report [ ((i + 2) * 8 + 7) : ((i + 2) * 8 + 0)] == kbd_code) begin if (report [i] == kbd_code_hid/*kbd_code*/) begin
report [ ((i + 2) * 8 + 7) : ((i + 2) * 8 + 0)] <= 0; report [i] = 0;
//report_free_place[i] = 1; isr = 1;
end end
end end
end end
//if (kbd_code == 8'h2C) begin
//if (is_pressed)
// report [15:8] <= kbd_code;
//else
// report [15:8] <= 0;
//end
//else if (kbd_code == 1) begin
// if (is_pressed)
// report [23:16] <= kbd_code;
// else
// report [23:16] <= 0;
//end
end end
end // END OF KBD CODE SEND ALG end // END OF KBD CODE SEND ALG
else else
isr <= 0; isr <= 0;
end
/*if (kbd_code != 0) begin
if (is_pressed)
report [7:0] <= kbd_code;
else
report [7:0] <= 0;
end*/
end end
end end
end end
assign kbd_report = report; task check_column;
assign INT = isr; input [2:0] column;
//assign ROWS_EN = (1 << row_counter); begin
if (COLS_SHADOW[column] != temp[column]) begin
kbd_code = row_counter*8 + column;
if ((COLS_SHADOW[column] == 0) && (temp[column] == 1)) is_pressed = 1;
else is_pressed = 0;
end
else kbd_code = 255;
temp[column] = COLS_SHADOW[column];
end
endtask
assign kbd_r0 = report[0];
assign kbd_r2 = report[1];
assign kbd_r3 = report[2];
assign kbd_r4 = report[3];
assign kbd_r5 = report[4];
assign kbd_r6 = report[5];
assign kbd_r7 = report[6];
assign INT = isr;
SB_RAM40_4K #(
.INIT_0(256'h0000_0001_0001_0001_00E7_0058_004C_0053__0001_0001_0001_0001_00E0_0039_00E1_0029), // ROW 0-1
.INIT_1(256'h0001_0001_0001_0001_002C_002A_0019_003B__0001_0001_0001_0001_00E2_0015_0006_003A), // ROW 2-3
.INIT_2(256'h0001_0001_0001_0001_002C_002A_0019_003B__0001_0001_0001_0001_00E2_0015_0006_003A), // ROW 4-5
.INIT_3(256'h0001_0001_0001_0001_002C_002A_0019_003B__0001_0001_0001_0001_00E2_0015_0006_003A), // ROW 6-7
.INIT_4(256'h0001_0001_0001_0001_002C_002A_0019_003B__0001_0001_0001_0001_00E2_0015_0006_003A), // ROW 8-9
.INIT_5(256'h0001_0001_0001_0001_002C_002A_0019_003B__0001_0001_0001_0001_00E2_0015_0006_003A), // ROW 10-11
.INIT_6(256'h0001_0001_0001_0001_002C_002A_0019_003B__0001_0001_0001_0001_00E2_0015_0006_003A), // ROW 12-13
.INIT_7(256'h0001_0001_0001_0001_002C_002A_0019_003B__0001_0001_0001_0001_00E2_0015_0006_003A), // ROW 14-15
.INIT_8(256'h0001_0001_0001_0001_002C_002A_0019_003B__0001_0001_0001_0001_00E2_0015_0006_003A), // ROW 16-17
.INIT_9(256'h0001_0001_0001_0001_002C_002A_0019_003B__0001_0001_0001_0001_00E2_0015_0006_003A), // ROW 18-19
.WRITE_MODE(1),
.READ_MODE(1)
) kbd_codes (
.RDATA(kbd_code_hid),
.RADDR(kbd_code),
.RCLK(CLK),
.RCLKE(1'b1),
.RE(1'b1),
.WADDR(8'b0),
.WCLK(1'b0),
.WCLKE(1'b0),
.WDATA(8'b0),
.WE(1'b0)
);
SB_IO #( SB_IO #(
.PIN_TYPE(6'b 1010_01), .PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 0) .PULLUP(1'b 0)
) rows_io [3:0] ( ) rows_io [15:0] (
.PACKAGE_PIN(ROWS), .PACKAGE_PIN(ROWS),
.OUTPUT_ENABLE(ROWS_EN), .OUTPUT_ENABLE(ROWS_EN),
.D_OUT_0(ROWS_OUT), .D_OUT_0(ROWS_OUT),

15
i2c_keyboard/ram.v
Unescape View File

@ -1,4 +1,4 @@
module ram(input clk, wen, input [8:0] addr, input [7:0] wdata, output [7:0] rdata); module ram(input clk, wen, input [8:0] waddr, input [7:0] wdata, input [8:0] raddr, output [7:0] rdata);
reg [7:0] mem [0:255]; reg [7:0] mem [0:255];
reg [7:0] r_data; reg [7:0] r_data;
reg [7:0] w_data; reg [7:0] w_data;
@ -6,13 +6,14 @@ module ram(input clk, wen, input [8:0] addr, input [7:0] wdata, output [7:0] rda
reg last_we; reg last_we;
initial mem[0] = 255; initial mem[0] = 255;
always @(posedge clk) begin always @(posedge clk) begin
if ((last_we == 0) && (wen == 1)) begin if (wen) begin //((last_we == 0) && (wen == 1)) begin
w_data = wdata; //w_data = wdata;
w_addr = addr; //w_addr = addr;
mem[w_addr] <= w_data; //mem[w_addr] <= w_data;
mem[waddr] <= wdata;
end end
r_data <= mem[addr]; r_data <= mem[raddr];
last_we = wen; //last_we = wen;
end end
assign rdata = r_data; assign rdata = r_data;

311
i2c_keyboard/top.v
Unescape View File

@ -2,16 +2,20 @@
module top (input CLK, output LED1, LED2, LED3, LED4, LED5, module top (input CLK, output LED1, LED2, LED3, LED4, LED5,
input SCL, inout SDA, /*output ACK,*/ output INTERRUPT, input SCL, inout SDA, /*output ACK,*/ output INTERRUPT,
input COM_RX, output COM_TX, COM_DCD, COM_DSR, COM_RTS, input COM_RX, output COM_TX, COM_DCD, COM_DSR, COM_RTS,
input [3:0] KBD_COLUMNS, inout [3:0] KBD_ROWS); input [7:0] KBD_COLUMNS, inout [15:0] KBD_ROWS);
wire RESET;
reg [3:0] rststate = 0;
assign RESET = &rststate;
//reg [7:0] I2C_TX; // TRANSMITTED TO MASTER //reg [7:0] I2C_TX; // TRANSMITTED TO MASTER
wire [7:0] I2C_TX; wire [7:0] I2C_TX;
reg [7:0] I2C_TX_DESC; reg [7:0] I2C_TX_DESC;
reg [7:0] I2C_TX_REPORT; //reg [7:0] I2C_TX_REPORT;
assign I2C_TX = (I2C_TX_DESC & I2C_OUT_DESC_MASK) | (I2C_TX_REPORT & (~I2C_OUT_DESC_MASK));
wire [7:0] I2C_RX; // RECEIVED FROM MASTER wire [7:0] I2C_RX; // RECEIVED FROM MASTER
wire I2C_TRANS, I2C_READ, I2C_ACK, I2C_ACK_MSTR_CTRL, I2C_WR; wire I2C_TRANS, I2C_READ, I2C_ACK, I2C_ACK_MSTR_CTRL, I2C_WR;
wire [9:0] I2C_COUNTER; wire [7:0] I2C_COUNTER;
i2c_slave I2C (CLK, RESET, SCL, SDA, I2C_TRANS, I2C_READ, I2C_ACK, I2C_WR, //I2C_ACK_MSTR_CTRL, i2c_slave I2C (CLK, RESET, SCL, SDA, I2C_TRANS, I2C_READ, I2C_ACK, I2C_WR, //I2C_ACK_MSTR_CTRL,
I2C_RX, I2C_TX, I2C_COUNTER); I2C_RX, I2C_TX, I2C_COUNTER);
@ -23,158 +27,273 @@ module top (input CLK, output LED1, LED2, LED3, LED4, LED5,
end end
uart UART (CLK, RESET, UART_WR, UART_TX_DATA, UART_ACTIVE, UART_TX_LINE); uart UART (CLK, RESET, UART_WR, UART_TX_DATA, UART_ACTIVE, UART_TX_LINE);
wire [63:0] kbd_report; //wire [63:0] kbd_report;
wire [7:0] kbd_report [6:0];
wire ISR; wire ISR;
reg INT = 1; // INTERRUPT LINE TO HOST reg INT = 1; // INTERRUPT LINE TO HOST
reg [19:0] int_tmr;
reg KBD_FREEZE = 1; // LOGIC REG FOR BLOCK KBD ACTIVITY WHEN I2C IS WORKING reg KBD_FREEZE = 1; // LOGIC REG FOR BLOCK KBD ACTIVITY WHEN I2C IS WORKING
reg IS_EMPTY_REPORT = 0; // REGISTER FOR CORRECT START (HOST MUST REQUEST EMPTY REGISTER AFTER INTERRUPT. THEN INTERRRUPT SET TO 1) //reg IS_EMPTY_REPORT = 0; // REGISTER FOR CORRECT START (HOST MUST REQUEST EMPTY REGISTER AFTER INTERRUPT. THEN INTERRRUPT SET TO 1)
matrix_kbd KEYBOARD (CLK, RESET, KBD_FREEZE, KBD_ROWS, KBD_COLUMNS, kbd_report, ISR); matrix_kbd KEYBOARD (CLK, RESET, 0 /*KBD_FREEZE*/, KBD_ROWS, KBD_COLUMNS, kbd_report[0], kbd_report[1], kbd_report[2], kbd_report[3], kbd_report[4], kbd_report[5], kbd_report[6], ISR);
descriptors I2C_HID_DESC (CLK, RESET, I2C_WR, I2C_OUTPUT_TYPE[1:0], I2C_COUNTER, I2C_TX_DESC/*, kbd_report*/); descriptors I2C_HID_DESC (CLK, RESET, I2C_WR, I2C_OUTPUT_TYPE[1:0], I2C_COUNTER, I2C_TX_DESC/*, kbd_report*/);
parameter MAX_INPUT_LEN = 10; //reg [7:0] ring_report [(8*8-1):0];
reg [7:0] I2C_INPUT_DATA [MAX_INPUT_LEN:0]; reg [7:0] init_ram_cnt;
reg [3:0] ring_wr, ring_rd;
reg [3:0] wr_cnt;
reg report_wr_en;
reg [7:0] report_data_wadr, report_data_radr, report_data_wr;
wire [7:0] report_data_rd;
ram REPORT_DATA (CLK, report_wr_en, report_data_wadr, report_data_wr, report_data_radr, report_data_rd);
assign I2C_TX = (I2C_TX_DESC & I2C_OUT_DESC_MASK) | (/*I2C_TX_REPORT*/report_data_rd & (~I2C_OUT_DESC_MASK));
//parameter MAX_INPUT_LEN = 10;
//reg [7:0] I2C_INPUT_DATA [MAX_INPUT_LEN:0];
reg [7:0] temp_output_report;
reg [3:0] i2c_input_data_type; // 0 - UNKNOWN, 1 - I2C_HID_DESC_REQUEST, 2 - HID_REPORT_DESC_REQUEST, 3 - INPUT_REPORT_REQUEST, 4 - OUTPUT_REPORT_SET
// 5 - RESET, 6 - GET_INPUT_REPORT, 7 - SET_OUTPUT_REPORT
reg [7:0] I2C_INPUT_LEN = 0; reg [7:0] I2C_INPUT_LEN = 0;
reg [2:0] I2C_OUTPUT_TYPE = 0; // 0 - ALL ZERO DATA, 1 - I2C HID DESCR, 2 - OUTPUT REPORT, 3 - HID REPORT DESCR reg [2:0] I2C_OUTPUT_TYPE = 0; // 0 - ALL ZERO DATA, 1 - I2C HID DESCR, 2 - OUTPUT REPORT, 3 - HID REPORT DESCR
reg [7:0] I2C_OUT_DESC_MASK = 0; reg [7:0] I2C_OUT_DESC_MASK = 0;
reg [7:0] KBD_LED_STATUS = 0; reg [7:0] KBD_LED_STATUS = 0;
reg last_wr = 0, last_trans = 0, last_uart_active = 0, last_isr = 0, uart_double_ff = 0; reg last_wr = 0, last_trans = 0, last_uart_active = 0, last_isr = 0, uart_double_ff = 0;
wire RESET;
reg [3:0] rststate = 0;
assign RESET = &rststate;
always @(posedge CLK) begin always @(posedge CLK) begin
// RESET LOGIC
rststate <= rststate + !RESET; rststate <= rststate + !RESET;
if (RESET == 0) begin if (RESET == 0) begin
I2C_OUTPUT_TYPE = 0; I2C_OUTPUT_TYPE = 3;//0;
I2C_OUT_DESC_MASK = 0; I2C_OUT_DESC_MASK = 0;
KBD_LED_STATUS = 0; // BIT 0 - NUM LOCK, BIT 1 - CAPS LOCK, BIT 2 - SCROOL LOCK KBD_LED_STATUS = 5; // BIT 0 - NUM LOCK, BIT 1 - CAPS LOCK, BIT 2 - SCROOL LOCK
uart_double_ff = 0; last_trans = 0; last_uart_active = 0; last_isr = 0;
I2C_INPUT_LEN = 0; I2C_INPUT_LEN = 0;
INT = 0; INT = 1; int_tmr = 0;
UART_WR = 0; UART_WR = 0;
KBD_FREEZE = 1; ring_wr = 0; ring_rd = 15; wr_cnt = 0;
IS_EMPTY_REPORT = 0; init_ram_cnt = 0;
end end
// NOT RESET MODE LOGIC
else begin else begin
if ((last_wr == 0) && (I2C_WR == 1)) begin if (init_ram_cnt < 170) begin
I2C_INPUT_LEN <= I2C_COUNTER - 1; report_wr_en = 1;
if (I2C_READ == 0) begin if (init_ram_cnt < 10)
if (I2C_COUNTER < (MAX_INPUT_LEN + 2)) report_data_wadr = 0;
I2C_INPUT_DATA[I2C_COUNTER - 2] <= I2C_RX; else
report_data_wadr = init_ram_cnt - 10;
report_data_wr = 0;//report_data_adr + 1;
init_ram_cnt = init_ram_cnt + 1;
end
else if (init_ram_cnt == 170) begin
report_wr_en = 0;
init_ram_cnt = init_ram_cnt + 1;
end
else if ((last_isr == 0) && (ISR == 1)/* && (INT == 1)*/) begin // INTERRUPT FROM KEYBOARD
if ((ring_wr + 1) != ring_rd)
ring_wr = ring_wr + 1;
report_wr_en = 1;
report_data_wadr = ring_wr * 10;
report_data_wr = 10;//kbd_report [0];
wr_cnt = 1;
INT = 0;
I2C_OUTPUT_TYPE = 3;
I2C_OUT_DESC_MASK = 8'h00;
last_isr = ISR;
end
else if ((last_isr == 1) && (ISR == 0))
last_isr = ISR;
else if (wr_cnt != 0) begin
if (wr_cnt == 10) begin
wr_cnt = 0;
report_wr_en = 0;
end end
else begin else begin
if (I2C_OUTPUT_TYPE == 3) begin report_data_wadr = ring_wr * 10 + wr_cnt;
if ((I2C_COUNTER < 2) || (I2C_COUNTER > (2 + 10 - 1))) if ((wr_cnt == 1) || (wr_cnt == 3))
I2C_TX_REPORT <= 0; report_data_wr = 0;
else if (I2C_COUNTER == 2) else if (wr_cnt == 2)
I2C_TX_REPORT <= 10; report_data_wr = kbd_report [wr_cnt - 2];
else if (I2C_COUNTER == 3)
I2C_TX_REPORT <= 0;
else else
I2C_TX_REPORT <= kbd_report[ (8 * (I2C_COUNTER - 4) + 7) : (8 * (I2C_COUNTER - 4) + 0) ]; report_data_wr = kbd_report [wr_cnt - 3];
wr_cnt = wr_cnt + 1;
end end
end
else if ((last_wr == 0) && (I2C_WR == 1)) begin // I2C NEW BYTE TX/RX
I2C_INPUT_LEN = I2C_COUNTER - 1;
if (I2C_READ == 0) begin // I2C_FROM_HOST
if (I2C_COUNTER == 2) begin
if ((I2C_RX > 5) || (I2C_RX < 1))
i2c_input_data_type = 0;
else else
I2C_TX_REPORT <= 0; i2c_input_data_type = I2C_RX;
end end
else if (I2C_COUNTER == 3) begin
if (I2C_RX != 0)
i2c_input_data_type = 0;
end end
else if ((last_wr == 1) && (I2C_WR == 0)) begin else if (I2C_COUNTER == 4) begin
UART_WR <= 1; if (i2c_input_data_type == 5) begin
if (I2C_READ == 0) case (I2C_RX) 0: i2c_input_data_type = 5; 16: i2c_input_data_type = 6;
UART_TX_DATA <= I2C_RX; 32: i2c_input_data_type = 7; default: i2c_input_data_type = 0; endcase
else
UART_TX_DATA <= I2C_TX;
end end
else if ((last_trans == 0) && (I2C_TRANS == 1)) begin
UART_TX_DATA = 8'hFF;
UART_WR = 1;
uart_double_ff = 1;
KBD_FREEZE = 0;
end end
else if ((last_trans == 1) && (I2C_TRANS == 0)) begin else if (I2C_COUNTER == 5) begin
if (I2C_READ == 0) begin // DECODING PACKET RECEIVED FROM HOST if (((i2c_input_data_type == 5) && (I2C_RX != 1)) || ((i2c_input_data_type == 6) && (I2C_RX != 2)) || ((i2c_input_data_type == 7) && (I2C_RX != 3)))
if (I2C_INPUT_LEN == 0) i2c_input_data_type = 0;
KBD_FREEZE <= 0;
else if (I2C_INPUT_LEN == 2) begin
if ((I2C_INPUT_DATA[0] == 1) && (I2C_INPUT_DATA[1] == 0)) // I2C_HID_DESC_REQUEST
I2C_OUTPUT_TYPE = 1;
else if ((I2C_INPUT_DATA[0] == 2) && (I2C_INPUT_DATA[1] == 0)) // HID REPORT DESC REQUEST
I2C_OUTPUT_TYPE = 2;
else if ((I2C_INPUT_DATA[0] == 3) && (I2C_INPUT_DATA[1] == 0)) // INPUT REPORT REQUEST (ADR)
I2C_OUTPUT_TYPE = 3;
//else
// I2C_OUTPUT_TYPE = 0; //
end end
else if (I2C_INPUT_LEN == 5) begin // OUTPUT REPORT SET (LEDS) - WRITE TO OUT ADR else if (I2C_COUNTER == 6) begin
if ((I2C_INPUT_DATA[0] == 4) && (I2C_INPUT_DATA[1] == 0) && (I2C_INPUT_DATA[2] == 1) && (I2C_INPUT_DATA[3] == 0)) begin if (i2c_input_data_type == 4)
KBD_LED_STATUS <= I2C_INPUT_DATA[4]; temp_output_report = I2C_RX;
KBD_FREEZE <= 0; else if (((i2c_input_data_type == 6) || (i2c_input_data_type == 7)) && (I2C_RX != 6))
i2c_input_data_type = 0;
end end
//else else if (I2C_COUNTER == 7) begin
// I2C_OUTPUT_TYPE = 0; // if (((i2c_input_data_type == 6) || (i2c_input_data_type == 7)) && (I2C_RX != 0))
i2c_input_data_type = 0;
end end
else if (I2C_INPUT_LEN == 6) begin // INPUT REPORT REQUEST (KBD PRESS INFO) else if (I2C_COUNTER == 10) begin
if ((I2C_INPUT_DATA[0] == 5) && (I2C_INPUT_DATA[1] == 0) && (I2C_INPUT_DATA[2] == 16) && (I2C_INPUT_DATA[3] == 2) && (I2C_INPUT_DATA[4] == 6) && (I2C_INPUT_DATA[5] == 0)) if (i2c_input_data_type == 7)
I2C_OUTPUT_TYPE = 3; temp_output_report = I2C_RX;
//else
// I2C_OUTPUT_TYPE = 0; //
end end
else if (I2C_INPUT_LEN == 9) begin // OUTPUT REPORT SET (LEDS) - WRITE BY CMD
if ((I2C_INPUT_DATA[0] == 5) && (I2C_INPUT_DATA[1] == 0) && (I2C_INPUT_DATA[2] == 32) && (I2C_INPUT_DATA[3] == 3) && (I2C_INPUT_DATA[4] == 6) && (I2C_INPUT_DATA[5] == 0) /*&& (I2C_INPUT_DATA[6] == 1) && (I2C_INPUT_DATA[7] == 0)*/) begin
KBD_LED_STATUS <= I2C_INPUT_DATA[8];
KBD_FREEZE <= 0;
end end
//else
// I2C_OUTPUT_TYPE = 0; // else begin // I2C_TO_HOST
if (I2C_OUTPUT_TYPE == 3) begin
//if ((I2C_COUNTER < 2) || (I2C_COUNTER > (2 + 10 - 1)))
// I2C_TX_REPORT <= 0;
/*else */if (I2C_COUNTER == 2) begin
if (ring_rd != ring_wr)
ring_rd = ring_rd + 1;
report_data_radr = ring_rd * 10;
end end
else if (I2C_INPUT_LEN == 4) begin else
if ((I2C_INPUT_DATA[0] == 5) && (I2C_INPUT_DATA[1] == 0) && (I2C_INPUT_DATA[2] == 0) && (I2C_INPUT_DATA[3] == 1)) report_data_radr = report_data_radr + 1;
rststate <= 4'h0; // RESET COMMAND //else if (I2C_COUNTER == 2)
// I2C_TX_REPORT <= 10;
//else if ((I2C_COUNTER == 3) || (I2C_COUNTER == 5)) begin
// I2C_TX_REPORT <= 0;
// if (ring_rd != ring_wr)
// ring_rd = ring_rd + 1;
// report_data_radr = ring_rd * 10;
//end
/*else if (I2C_COUNTER == 4)
I2C_TX_REPORT <= kbd_report[0];*/
//else begin
// I2C_TX_REPORT = report_data_rd;
// report_data_radr = report_data_radr + 1;
//I2C_TX_REPORT <= kbd_report[I2C_COUNTER - 5];
//end
end end
//else //else
// I2C_OUTPUT_TYPE = 0; // // I2C_TX_REPORT <= 0;
end
last_wr = I2C_WR;
end // I2C NEW BYTE TX/RX - END
else if ((last_wr == 1) && (I2C_WR == 0)) begin // I2C_NEW_BYTE_NEGEDGE_FOR_UART
UART_WR = 1;
if (I2C_READ == 0)
UART_TX_DATA = I2C_RX;
else
UART_TX_DATA = I2C_TX;
last_wr = I2C_WR;
end // I2C_NEW_BYTE_NEGEDGE_FOR_UART - END
else if ((last_trans == 0) && (I2C_TRANS == 1)) begin // I2C_START_CONDITION OR REPEAT START (UART FF)
i2c_input_data_type = 0; // UNKNOWN DATA IN
uart_double_ff = 1;
UART_TX_DATA = 8'hFF;
UART_WR = 1;
last_trans = I2C_TRANS;
end // I2C_START_CONDITION (UART FF) - END
else if ((last_trans == 1) && (I2C_TRANS == 0)) begin // I2C_STOP CONDITION (OR REPEAT START DETECTED)
KBD_FREEZE <= 0;
if (I2C_READ == 0) begin // DECODING PACKET RECEIVED FROM HOST
if (((i2c_input_data_type < 4) && (I2C_INPUT_LEN != 2)) || ((i2c_input_data_type == 4) && (I2C_INPUT_LEN != 5)) || ((i2c_input_data_type == 5) && (I2C_INPUT_LEN != 4)) || ((i2c_input_data_type == 6) && (I2C_INPUT_LEN != 6)) || ((i2c_input_data_type == 7) && (I2C_INPUT_LEN != 9)))
i2c_input_data_type = 0;
if ((i2c_input_data_type == 1) || (i2c_input_data_type == 2) || (i2c_input_data_type == 3))
I2C_OUTPUT_TYPE = i2c_input_data_type;
else if ((i2c_input_data_type == 4) || (i2c_input_data_type == 7))
KBD_LED_STATUS = temp_output_report;
else if (i2c_input_data_type == 6)
I2C_OUTPUT_TYPE = 3;
else if (i2c_input_data_type == 5)
rststate <= 4'h0; // RESET COMMAND
if ((I2C_OUTPUT_TYPE == 1) || (I2C_OUTPUT_TYPE == 2)) if ((I2C_OUTPUT_TYPE == 1) || (I2C_OUTPUT_TYPE == 2))
I2C_OUT_DESC_MASK = 8'hFF; I2C_OUT_DESC_MASK = 8'hFF;
else else
I2C_OUT_DESC_MASK = 8'h00; I2C_OUT_DESC_MASK = 8'h00;
end // END OF I2C_READ == 0 end // END OF I2C_READ == 0
else begin else begin
KBD_FREEZE <= 0; // UNFREEZING KBD AFTER ANYONE I2C RECEIVING if (((I2C_OUTPUT_TYPE == 3) /*|| (I2C_OUTPUT_TYPE == 0)*/) && (I2C_INPUT_LEN > 1)) begin
//if (((I2C_OUTPUT_TYPE == 3) && (I2C_INPUT_LEN == 10)) || ((I2C_OUTPUT_TYPE == 0) && (I2C_INPUT_LEN > 1))) begin // HARD
if (((I2C_OUTPUT_TYPE == 3) || (I2C_OUTPUT_TYPE == 0)) && (I2C_INPUT_LEN > 1)) begin // SOFT
// DEACTIVATING INTERRRUPT IF HOST READ INPUT REPORT (LEN 10) AFTER INTERRUPT OR EMPTY DATA (>=2 BYTES) AFTER RESET // DEACTIVATING INTERRRUPT IF HOST READ INPUT REPORT (LEN 10) AFTER INTERRUPT OR EMPTY DATA (>=2 BYTES) AFTER RESET
// AND UNFREEZING KEYBOARD //if (ring_rd == ring_wr)
INT <= 1; INT = 1;
//KBD_FREEZE <= 0; int_tmr = 0;
IS_EMPTY_REPORT = 1;
end //if (ring_rd != ring_wr)
// ring_rd = ring_rd + 1;
end end
I2C_OUTPUT_TYPE = 3;
I2C_OUT_DESC_MASK = 0;
end end
else if ((last_uart_active == 1) && (UART_ACTIVE == 0) && (uart_double_ff == 1)) begin last_trans = I2C_TRANS;
end // I2C_STOP CONDITION (OR REPEAT START DETECTED) - END
else if ((last_uart_active == 1) && (UART_ACTIVE == 0)) begin
if (uart_double_ff == 1) begin
UART_WR = 1; UART_WR = 1;
UART_TX_DATA = 8'hFF; UART_TX_DATA = 8'hFF;
uart_double_ff = 0; uart_double_ff = 0;
I2C_INPUT_LEN = 0;
end end
last_uart_active = UART_ACTIVE;
end
else if ((last_uart_active == 0) && (UART_ACTIVE == 1))
last_uart_active = UART_ACTIVE;
else if (UART_WR == 1) else if (UART_WR == 1)
UART_WR <= 0; UART_WR = 0;
else if ((last_isr == 0) && (ISR == 1) && (INT == 1)) begin
else if (int_tmr[19] != 1)
int_tmr = int_tmr + 1;
else if ((int_tmr[19] == 1) && (I2C_OUTPUT_TYPE == 3) && (I2C_TRANS == 0)) begin
if (ring_rd != ring_wr)
INT = 0; INT = 0;
I2C_OUTPUT_TYPE = 3;
I2C_OUT_DESC_MASK = 8'h00;
end end
last_wr <= I2C_WR; /*else if (wr_cnt != 0) begin
last_trans <= I2C_TRANS; ring_report[ring_wr * 8 + wr_cnt] <= kbd_report[ (8 * wr_cnt + 7) : (8 * wr_cnt + 0) ];
last_uart_active <= UART_ACTIVE; wr_cnt = wr_cnt + 1;
last_isr <= ISR; // if (wr_cnt == 0) // START ISR
end*/
end end
end end
assign LED5 = I2C_TRANS; assign LED5 = I2C_TRANS;
//assign LED5 = COM_RX; //assign LED5 = COM_RX;
assign LED1 = INT ^ 1;//KBD_COLUMNS[0];//I2C_OUTPUT_TYPE[0];//I2C_RX[0]; assign LED1 = INT ^ 1;//KBD_COLUMNS[0];//I2C_OUTPUT_TYPE[0];//I2C_RX[0];
assign LED2 = KBD_LED_STATUS[0];//I2C_OUTPUT_TYPE[0]; //assign LED2 = I2C_OUTPUT_TYPE[0];
assign LED3 = KBD_LED_STATUS[1];//I2C_OUTPUT_TYPE[1]; //assign LED3 = I2C_OUTPUT_TYPE[1];
assign LED2 = KBD_LED_STATUS[0];
assign LED3 = KBD_LED_STATUS[1];
assign LED4 = KBD_LED_STATUS[2];//KBD_FREEZE;//UART_ACTIVE; assign LED4 = KBD_LED_STATUS[2];//KBD_FREEZE;//UART_ACTIVE;
//assign LED3 = UART_ACTIVE;
//assign LED4 = uart_double_ff;
//assign ACK = I2C_READ;//I2C_WR; //I2C_ACK; //assign ACK = I2C_READ;//I2C_WR; //I2C_ACK;
assign COM_TX = UART_TX_LINE;//COM_RX; assign COM_TX = UART_TX_LINE;//COM_RX;

4
i2c_keyboard/uart.v
Unescape View File

@ -8,7 +8,9 @@ module uart ( input CLK, input RESET, input TX_SIGNAL, input [7:0] TX_BYTE,
// IF BYTE IS TRANSMITTING, ATTEMPT TO TRANSMIT OTHER BYTE HAS NO EFFECT // IF BYTE IS TRANSMITTING, ATTEMPT TO TRANSMIT OTHER BYTE HAS NO EFFECT
// MODULE WORKS AT POSEDGE // MODULE WORKS AT POSEDGE
parameter CLK_DIV = 13; parameter CLK_DIV = 13; // 921600
//parameter CLK_DIV = 5000; // 2400
//parameter CLK_DIV = 104; // 115200
reg TX_sig_last; reg TX_sig_last;
reg [3:0] tx_bit_counter; reg [3:0] tx_bit_counter;
reg [3:0] tx_clk_counter; // MUST CONTAIN CLK DIV reg [3:0] tx_clk_counter; // MUST CONTAIN CLK DIV

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