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# ULX3S PCB
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This is work-in-progress place for putting
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some wishes of a small (94x51 mm) FPGA board.
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ULX3S = University digital logic Learning eXtensible
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board release 3 with SDRAM, Successor of ULX2S.
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kicad ulx3s.pro
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[Schematics](/doc/schematics.pdf) is mostly complete.
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PCB routing is mostly complete too.
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3D preview
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# Features
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FPGA: Lattice ECP5 LFE5U-25F-6BG381C
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USB: FTDI FT231XS (1Mbit JTAG and 3Mbit usbserial)
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GPIO: All differential, PMOD-friendly
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RAM: 32MB SDRAM MT48LC16M16
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Flash: 8MB SPI flash S25FL164 for FPGA config
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Storage: Micro-SD slot
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LEDs: 10 (8 blink-LEDs, 2 USB leds)
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Buttons: 7 (4 direction, 2 fire, 1 power button)
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Audio: 3.5 mm jack with 4 contacts (analog stereo + digital audio or composite video)
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Video: GPDI connector with 3.3V-5V I2C bidirectional level shifter
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Display: placeholder for 0.96-1.3" SPI OLED COLOR or B/W
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WiFi+bluetooth: placeholder for ESP-32 (JTAG and serial over WiFi possible)
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ADC: 8 channels, 12 bit, 1 MSa/s MAX11123
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Power: 3 Switching voltage regulators: 1.2V, 2.5V, 3.3V
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Clock: 25 MHz onboard, external differential clock input
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Low power sleep: RTC clock wakeup, power button, 32768 Hz quartz and battery
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GPDI is General Purpose Differential Interface,
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Electrically LVDS, mostly TMDS tolerant
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female receptacle more-or-less compatible
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with digital monitors/TVs
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# Todo
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Make the prototype.
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[x] Silkscreen Double outline for BGA chip
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[x] Silkscreen do not write over the solder pads
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[ ] Silkscreen BGA names on ESP32 placeholder and 2.54 mm headers
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[x] Silkscreen JTAG signal names on 6-pin 2.54 mm header
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[x] Silkscreen remove OLED outline
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[x] Solder stop mask must go inbetween all SMD chip pads
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[x] External differential clock input at J1_33 +/-
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[ ] Thinner copper, more spacing to SDRAM-FPGA
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[x] physically sprinkle VCC blocator capacitors under BGA
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[ ] Values on silkscreen
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[x] Dedicated antenna pin
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[x] onboard 433 antenna
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[x] 433 remove GND and silkscreen test point
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[x] Resistors for LEDs
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[x] Move USB LEDs from bottom to top side
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[x] Improve SDRAM routing - use VIAs for closest pins
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[x] Increase thickness of power lines (5V, 3.3V, 2.5V)
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[x] Compile a f32c bitstream using the schematics
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[x] Compile differential GPDI output
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[x] Connect more lines from ESP-32 to FPGA
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[x] Connect FPGA USB D+/D- with 1.5k pullup in USB 1.1 (full speed) mode
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[x] FPGA USB add 27 ohm + 3.6 V zener
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[x] Symmetrically place USB connectors left-right
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[ ] Jumpers to switch 2.5V/3.3V for left IO banks
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[x] External JTAG header
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[x] Move JTAG 2 mm left
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[x] Move WiFi Disable jumper closer to the BTN1 (angled header)
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[x] Sprinkle 2.2uF capacitors on power lines
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[x] Spice simulation of power-up/shutdown network
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[x] 27ohm D+/D- to FT231XS
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[x] DIP switch (4 switches)
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[x] MAX11123 ADC SPI
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[x] I2C for RTC
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[x] main usb connector on top side
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[ ] space screw to other parts
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[x] move battery away from screw hole
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[x] top layer GND fill
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[x] R25 move away from oled screw hole
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[ ] board cut off nothches inisde for space saving
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[x] DIP switch to the right near RAM
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[x] Move HDMI a bit closer to OLED
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[x] 32768Hz oscillator footprint
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[x] SD card footprint SCHD3A0100
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[ ] SD use CD (card detect) contacts
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[x] move USB 0.5-1mm more out
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[x] DIP SW footprint correct
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[x] AUDIO jack footprint fits
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[x] AUDIO jack pin 4 (ring2) connected to 4-bit DAC
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[x] BTN footprint too small
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[x] SMPS jumpers default OFF for prototype testing
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[x] FPGA DONE to ESP-32
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[x] Diodes manual soldering
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[x] R56: FT231X rev A,B,C TXDEN to GND
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workaround from TN140_FT231X Errata
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[x] PCB for LFE5UM ready (some GND will change to
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VCC for Serdes power supply, see LFE5U->LFE5UM
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migration docs)
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[x] Check GND/VCC for 45 and 85 packages,
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for example pin T11 is NC on 25U, GND on 85U and VCC ond 85UM
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