42e3255b7a
schematics: US2 diodes pull up/down 1.5k/15k
7 years ago
d95e2eab3d
schematics: 3 decoupling 22nF capacitors for SDRAM
7 years ago
2f3cc59274
schematics: adding mouser P/N
7 years ago
b205d52f4f
schematics: sprinkling 22nF decoupling capacitors under FPGA
7 years ago
a04b74cc61
schematics, footprints: micro usb cleanup
7 years ago
6079a51257
schematics: symbol for SDRAM copied from rescue to proper library
7 years ago
c1053dd7bd
schematics: cleanup of MFG_PN to simplify BOM
7 years ago
6b50f65544
footprints: FPGA renaming Quad SPI lines D2,D3
...
schematics: reference FPGA footprint directly (not from rescue file)
7 years ago
987aefa1fd
schematics: routing FPGA to SPI QUAD.
...
BTN_R,U connected to BANK2,3 on "ram" sheet
7 years ago
e81d05b68d
schematics: renaming pins J..+- to GP,GN..
7 years ago
91dc09995c
schematics: SDRAM manufacturer url and PN
7 years ago
11e38d2211
schematics: corrected SDRAM part number
7 years ago
f5de9a85ed
schematics: connecting SHUTDOWN to FPGA
7 years ago
f4d7692c91
schematics: SD card symbol with 2 CD pins connected to GND
7 years ago
537e2229b6
schematics: swap U2,U9
7 years ago
3915779e0c
schematics: part numbers and URLs of datasheets and manufacturers
...
of most chips and connectors. Small parts not done yet.
7 years ago
52814d6ae0
WIFI LED (blue) on schematics
7 years ago
a5a51a8f28
connected missing SD card pins to esp-32
7 years ago
cca17d282d
open-close to check that everything loads fine
7 years ago
35b3a8b3dd
changing to 45F which is production device now
...
schem symbol 45F fixed typo T8->T7 (GND) and SERDES
7 years ago
ba4c8e8d22
PCB v1.6 SDRAM fully reworked
7 years ago
1ea88bda53
Adding pins to schematic symbols for all chips in unit "H" (SERDES)
...
Non-serdes chips need GND connection on unit "H".
"power" sheet now connects GND's at unit "H".
7 years ago
d57b16519c
update (I hope) all chip units to 85F
...
add more GND vias
7 years ago
e4fc99887e
moving GND and VCC on schematics symbols to
...
common locations for planned PCB which
supports upgrade path for example
12F->25F->45F->85F and if possible ECP5U->ECP5UM
7 years ago
07de158d38
R56 for FT231X rev A,B,C workaround from TN140_FT231X Errata
7 years ago
bc4b88ee58
Micro SD: using SCHD3A0100
7 years ago
10df092413
using modified ECP5 footprint
7 years ago
bab7ee607e
placeholder for 1.5k pullup for usb 1.0
7 years ago
f120d212d9
433 MHz onboard antenna (need to uncover copper infill layers)
7 years ago
0229a768ad
FPGA direct-to-pin Hackish USB transciver 27 ohm + 3.6 V zener
7 years ago
5f589c33f4
USB directly to FPGA for possible USB1.1 core
7 years ago
6d14ed8ff0
Placing DIP switch, but not yet connecting it to FPGA
7 years ago
37bb008e24
ADC connecting REF+/REF- and SPI
7 years ago
2153a220a0
schematic symbol for ADC MAX11123
...
small PCB traces cleanup
ADC chip placed on PCB but connected only to GND
7 years ago
be09416928
Add 27 ohm resistors in series with FTDI USB and readme update
8 years ago
278ac6b341
2.2uF for ESP-32 and gerber update
8 years ago
ee7d266543
Resistors for LEDs
8 years ago
18aef04f2c
JTAG header
8 years ago
dcbf46dff2
optimizing PCB
8 years ago
b7500cc477
increasing thickness of power traces, moving clock
...
to a bank which is always at 3.3V
8 years ago
2a60828a99
schem. pullup 1.5k for USB 1.1 full speed mode
8 years ago
23b588ff16
Routing... 4 routes remaining
8 years ago
0f9d00f602
Buffer capacitor for SDRAM
8 years ago
1e5e0b01a6
connecting JTAG lines to FTDI serial lines RI DCD CTS DSR
...
as those pins are by default inputs and can be reconfigured as outputs
similar but not identical pinout as the one that works from ujprog
CBUS used to force-wakeup of the board from sleep state
2 LEDs to CBUS pins to display usb enumeration and activity status
8 years ago
dcc2d375ea
routing additional pins to J2 GPIO. 2 differential pairs left to route
8 years ago
9f0d9c46a7
routing half of J2 gpio
8 years ago
e30bbeea40
routing 4 GPIO on J2
8 years ago
19b884baef
using corrected schem symbol, reordering pins
8 years ago
39dce76f0a
use new schem symbol
8 years ago
a8f1214b27
reorder SDRAM to FPGA connection for straightforward routing
8 years ago
davor