|  Davor | f894f386df | design rules, move to BGA netlist to route with thinner traces | 9 years ago | 
				
					
						|  Davor | 12e89e677a | connecting wifi, usbserial, oled, sd card | 9 years ago | 
				
					
						|  Davor | 0ca9b4cb0e | notify possible extra width of the board 7x2.54 mm that would fit into protoboard | 9 years ago | 
				
					
						|  Davor | 3e68526ccb | it acutally routed but schematic is still incomplete :) After freeroute overnight run, DRC complained only for
tracks too close to holes or vias and that is easy to
manually fix | 9 years ago | 
				
					
						|  Davor | 498701d2b4 | gitignore intermediate files of freeroute | 9 years ago | 
				
					
						|  Davor | 4a63816ba2 | remove freeroute intermediate file | 9 years ago | 
				
					
						|  Davor | ad0ae760b5 | overnight run of freeroute routed much but couldn't route it all | 9 years ago | 
				
					
						|  Davor | a477fbd050 | connecting flash config chip | 9 years ago | 
				
					
						|  davor | a8c293805f | moving battery down, partially routed | 9 years ago | 
				
					
						|  davor | dc1ae11172 | partially routed board using "freeroute" autorouter | 9 years ago | 
				
					
						|  davor | e37f17e390 | moving PCB components around | 9 years ago | 
				
					
						|  davor | 2dedab2d9a | moving 8-pin chip away from 3.5mm jack | 9 years ago | 
				
					
						|  davor | 9b02f3265d | compacting the board to hold 2.54mm headers, buttons moved randomly just to fit | 9 years ago | 
				
					
						|  davor | 85cb0b3f93 | Placing 40-pin connectors side-by-side, changing ft2232 to ft231x | 9 years ago | 
				
					
						|  davor | 5221d8270a | add footprint for several ftdi usbserial chip including FT231X | 9 years ago | 
				
					
						|  davor | 2de9717740 | fpga bga schematic symbol set exact chip name | 9 years ago | 
				
					
						|  davor | a7de1a4e58 | power button | 9 years ago | 
				
					
						|  davor | 5d5a4031cc | pins VREF named on schematic symbol of fpga | 9 years ago | 
				
					
						|  davor | a60712b2f6 | place renumbered schematic units of the fpga chip | 9 years ago | 
				
					
						|  davor | 067962ec48 | fpga schematic symbol: renumbering bank units | 9 years ago | 
				
					
						|  davor | e2899667ef | place all available banks to gpio page | 9 years ago | 
				
					
						|  davor | 4d31d658fb | Added pins for remaining banks. Need to verify if everything is correct. | 9 years ago | 
				
					
						|  davor | c3889467a0 | rename gpio pins same as BGA pin e.g. A9, C11, ... | 9 years ago | 
				
					
						|  davor | 4f3fabdb5f | oled updated on the schematic and PCB | 9 years ago | 
				
					
						|  davor | 27e311a270 | improving oled pcb footprint | 9 years ago | 
				
					
						|  davor | 4626f7a0e3 | oled schematic symbol | 9 years ago | 
				
					
						|  davor | b1062e5795 | place oled symbol on pcb | 9 years ago | 
				
					
						|  davor | 650c95b52b | oled pinput | 9 years ago | 
				
					
						|  davor | 9edeb3ae1e | oled footprint | 9 years ago | 
				
					
						|  davor | 6639abded3 | add 4 mounting holes | 9 years ago | 
				
					
						|  davor | b661cacede | Change to 2x20 pin headers, PCB layout currently sub-optimal | 9 years ago | 
				
					
						|  davor | f7185a0ff7 | improving wifi SD and JTAG pinouts. Unsure of JTAG (GPIO20 is NC on ESP-32S module?) | 9 years ago | 
				
					
						|  davor | e50f754eb4 | esp32 module pinout | 9 years ago | 
				
					
						|  davor | f9ba6fa20b | chage ESP8266-12E to ESP32S approximate (maybe incorrect) connections - need review
(programming esp from fpga, jtag, sd, chip enable) | 9 years ago | 
				
					
						|  davor | a0dae5bb6a | another diode to duscharge C14 at shutdown | 9 years ago | 
				
					
						|  Davor | cf01d5cc8d | Power: Replace discharge resistor which leaks with a diode for discharge C at shutdown
HDMI pin 0 is now the shield and connected to GND | 9 years ago | 
				
					
						|  Davor | 75375ac1e8 | readme update | 9 years ago | 
				
					
						|  Davor | 7b1ce8fc93 | readme update | 9 years ago | 
				
					
						|  Davor | f9e8652943 | readme update | 9 years ago | 
				
					
						|  Davor | 0c9d9f0c10 | readme update | 9 years ago | 
				
					
						|  Davor | f6e80bdd12 | readme update | 9 years ago | 
				
					
						|  Davor | a79dba2e5e | readme update | 9 years ago | 
				
					
						|  Davor | 8110cea7fa | moving DAC resistor network closer to 3.5mm jack | 9 years ago | 
				
					
						|  davor | 5d4ce79295 | connecting BANK2 to PMOD connectors | 9 years ago | 
				
					
						|  davor | b62dc97d89 | adding BANK2 pins to FPGA shematic symbol | 9 years ago | 
				
					
						|  davor | dc6ea57d67 | Label button pullup net "BTNPU" | 9 years ago | 
				
					
						|  davor | 222f4805b3 | SDRAM add global labels for signals | 9 years ago | 
				
					
						|  davor | 23c4cde741 | GPDI I2C 5V level shifter | 9 years ago | 
				
					
						|  davor | 9132d32bc8 | gerber update | 9 years ago | 
				
					
						|  davor | 7fd0f561fc | Add SPI flash chip | 9 years ago |