It will sometimes NAK part-way through a multi-packet OUT URB. And what
it wants is for the host to resend beginning from the last even-numbered
packet. NOT the last packet it received, and NOT the beginning of that
URB.
It turned out we were getting a "device disconnected" interrupt while
waiting for the port to enable following reset. Simply ignoring the
disconnect interrupt allows everything to work! WTF...
...Downstream was not always changing state correctly after closely
spaced interrupts.
Also improve flash-write-lockout function to avoid dependency on
optimisation level.
Conflicts:
Upstream/Src/interrupts.c
Each USB transaction passed to the driver now consists of multiple
64-byte packets. 8 packets when receiving, 4 packets when transmitting.
The STM32 silicon bugs out when more than 4 packets are scheduled to
write at a time :(
Reads 1.0MB/sec, writes 967kB/sec, not CPU limited :)
Added timeout checks and retry functionality to control transaction
state machine. But some times the device just won't talk, so we flash
the fault LED slowly to give the user some clue about what happened.
- Unexpected second port-connected interrupt on cold boot with low-speed
device connected.
- Retry on failure to get device descriptor. (We still fail after three
attempts, but that is better than failing after the first one!)
Also changed eclipse project to use external builder.
Our custom OpenOCD scripts are now linked directly into the Eclipse debug configurations.
No need to manually copy the files into OpenOCD's script directory.
Our custom OpenOCD scripts are now linked directly into the Eclipse
debug configurations. No need to manually copy the files into OpenOCD's
script directory.
some flash drives can take up to 2 seconds to write a single block.
Also, reverting the previous two commits because they didn't actually
help. Aughhhhhh...
So there's a host controller hardware bug on the STM32F407 that
manifests when writing to some FAT filesystems. Transactions will stop
partway through a 512-byte write, and nothing can get them started
again. We can avoid this by soft-resetting the AHB-interface state
machines on every channel halt.
some circumstances the 405 is equally buggy as the 401!
Work around an intermittent stall/timeout by busy-waiting Upstream's
packet length transmission and reception, instead of DMA-ing it like the
packet body. Ugh...
Robert Fisk