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i2c_keyboard update

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master
Ivan Olenichev 6 years ago
parent 2c37e37bc3
commit 7d039e1c82
7 changed files with 9091 additions and 8099 deletions
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12
i2c_keyboard/Makefile
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@ -15,7 +15,17 @@ nextpnr: top.v inouts.pcf
icebox_explain i2c_kbd_alt.asc > i2c_kbd_alt.ex icebox_explain i2c_kbd_alt.asc > i2c_kbd_alt.ex
icepack i2c_kbd_alt.asc i2c_kbd_alt.bin icepack i2c_kbd_alt.asc i2c_kbd_alt.bin
burn:
iceprog -d i:0x0403:0x6010 i2c_kbd_alt.bin
burn0:
iceprog -d i:0x0403:0x6010:0 i2c_kbd_alt.bin
burn1:
iceprog -d i:0x0403:0x6010:1 i2c_kbd_alt.bin
clean: clean:
rm -f i2c_kbd_alt.blif i2c_kbd_alt.asc i2c_kbd_alt.ex i2c_kbd_alt.bin i2_kbd_alt.json rm -f i2c_kbd_alt.blif i2c_kbd_alt.asc i2c_kbd_alt.ex i2c_kbd_alt.bin i2_kbd_alt.json
#icetime -tmd hx1k i2c_kbd_alt.asc time:
icetime -tmd hx1k i2c_kbd_alt.asc

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i2c_keyboard/i2c_kbd_alt.bin
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i2c_keyboard/i2c_kbd_alt.blif
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i2c_keyboard/i2c_kbd_alt.ex
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2
i2c_keyboard/inouts.pcf
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@ -16,7 +16,6 @@ set_io CLK 21
set_io SCL 90 # J2, 9 set_io SCL 90 # J2, 9
set_io SDA 91 # J2, 10 set_io SDA 91 # J2, 10
set_io INTERRUPT 88 # J2, 8 set_io INTERRUPT 88 # J2, 8
#set_io INTERRUPT_INVERT 87 #J2-7 or PIO1-06
# GND - J2, 11 # GND - J2, 11
#set_io INT 95 #set_io INT 95
@ -48,7 +47,6 @@ set_io KBD_ROWS[10] 80 #J2-3 or PIO1-04
set_io KBD_ROWS[11] 81 #J2-4 or PIO1-05 set_io KBD_ROWS[11] 81 #J2-4 or PIO1-05
set_io KBD_ROWS[12] 87 #J2-7 or PIO1-06 set_io KBD_ROWS[12] 87 #J2-7 or PIO1-06
#set_io KBD_ROWS[12] 41
set_io KBD_ROWS[13] 37 #PIO2-04 set_io KBD_ROWS[13] 37 #PIO2-04
set_io KBD_ROWS[14] 38 #PIO2-05 set_io KBD_ROWS[14] 38 #PIO2-05

293
i2c_keyboard/matrix_kbd.v
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@ -1,5 +1,5 @@
module matrix_kbd ( input CLK, input RESET, input FREEZE, inout [15:0] ROWS, input [7:0] COLUMNS, module matrix_kbd ( input CLK, input RESET, input FREEZE, inout [15:0] ROWS, input [7:0] COLUMNS,
input [3:0] REPORT_ADRESS, output [7:0] REPORT_DATA, output INT); input [3:0] REPORT_ADRESS, output [7:0] REPORT_DATA, output INT, output DBG);
//output [7:0] kbd_r0, kbd_r2, kbd_r3, kbd_r4, kbd_r5, kbd_r6, kbd_r7, output INT); //output [7:0] kbd_r0, kbd_r2, kbd_r3, kbd_r4, kbd_r5, kbd_r6, kbd_r7, output INT);
// * - ESC (29), 7 - F1 (3A), 4 - F2 (3B), 1 - NUM_LOCK (53) // * - ESC (29), 7 - F1 (3A), 4 - F2 (3B), 1 - NUM_LOCK (53)
@ -7,7 +7,7 @@ module matrix_kbd ( input CLK, input RESET, input FREEZE, inout [15:0] ROWS, inp
// # - LSHIFT (E1), 9 - C (06), 6 - V (19), 3 - DELETE (4C) // # - LSHIFT (E1), 9 - C (06), 6 - V (19), 3 - DELETE (4C)
// D - LCTRL (E0), C - LALT (E2), B - SPACE (2C), A - RGUI (E7) // D - LCTRL (E0), C - LALT (E2), B - SPACE (2C), A - RGUI (E7)
parameter ONE_ROW_TIME = 8000; parameter ONE_ROW_TIME = 12000;
parameter ROW_STT_PROCESS_TIME = 7000; parameter ROW_STT_PROCESS_TIME = 7000;
parameter ONE_COLUMN_PROCESS_TIME = 50; parameter ONE_COLUMN_PROCESS_TIME = 50;
parameter ONE_ROW_TIME_POW = 14; // 15 - 65536 tacts or 5.46 ms, 14 - 32768 tacts or 2.73 ms, 13 - 16384 tacts or 1.36 ms, parameter ONE_ROW_TIME_POW = 14; // 15 - 65536 tacts or 5.46 ms, 14 - 32768 tacts or 2.73 ms, 13 - 16384 tacts or 1.36 ms,
@ -15,12 +15,13 @@ module matrix_kbd ( input CLK, input RESET, input FREEZE, inout [15:0] ROWS, inp
// 7 - 256 tacts or 21 mks, other values have no guaranties // 7 - 256 tacts or 21 mks, other values have no guaranties
parameter ONE_CALC_TIME_POW = 4; // 3 - 16 tacts or 1.3 mks, 4 - 32 tacts or 2.7 mks, 5 - 64 tacts or 5.3 mks, 6 - 128 tacts or 10.7 mks parameter ONE_CALC_TIME_POW = 4; // 3 - 16 tacts or 1.3 mks, 4 - 32 tacts or 2.7 mks, 5 - 64 tacts or 5.3 mks, 6 - 128 tacts or 10.7 mks
// ONE_ROW_TIME_POW > (ONE_CALC_TIME_POW - 3); ONE_CALC_TIME_POW > 2 (if 2 or smaller, top module overrun may occur) // ONE_ROW_TIME_POW > (ONE_CALC_TIME_POW - 3); ONE_CALC_TIME_POW > 2 (if 2 or smaller, top module overrun may occur)
parameter CHATTERING_SUPRESSION_TIME = 100;
reg [ONE_ROW_TIME_POW:0] row_time = 0; reg [ONE_ROW_TIME_POW:0] row_time = 0;
reg [3:0] row_counter; reg [3:0] row_counter;
reg [7:0] temp; //reg [7:0] temp;
reg [7:0] i; //reg [7:0] i;
//reg [7:0] report [6:0]; // NO BYTE 2 //reg [7:0] report [6:0]; // NO BYTE 2
//reg [7:0] report_byte; //reg [7:0] report_byte;
@ -30,25 +31,25 @@ module matrix_kbd ( input CLK, input RESET, input FREEZE, inout [15:0] ROWS, inp
reg [15:0] ROWS_EN = 0; reg [15:0] ROWS_EN = 0;
reg [15:0] ROWS_OUT = 0; reg [15:0] ROWS_OUT = 0;
wire [15:0] ROWS_IN; wire [15:0] ROWS_IN;
reg [7:0] COLS_SHADOW; reg [7:0] COLUMN_SHADOW;
//reg [7:0] kbd_code; // reg [7:0] kbd_code;
wire [6:0] kbd_code; wire [6:0] kbd_code;
assign kbd_code [2:0] = row_time[7:5]; // COLUMN NUM assign kbd_code [2:0] = row_time[10:8]; // COLUMN NUM
assign kbd_code [6:3] = row_counter; // ROW NUM assign kbd_code [6:3] = row_counter; // ROW NUM
wire [7:0] kbd_code_hid; wire [7:0] kbd_code_hid;
reg is_pressed; reg is_pressed;
reg ram_wr; reg last_wr;
reg [8:0] ram_adr; reg [8:0] last_adr;
wire [7:0] ram_rd; wire [7:0] last_column;
//reg [3:0] init_delay_cnt; //reg [3:0] init_delay_cnt;
//reg [8:0] init_ram_cnt; //reg [8:0] init_ram_cnt;
reg IS_RAM_INIT = 0; reg IS_RAM_INIT = 0;
/*always @ (negedge CLK) begin /*always @ (negedge CLK) begin
COLS_SHADOW <= COLUMNS; COLUMN_SHADOW <= COLUMNS;
end*/ end*/
wire [7:0] report_data_rd; wire [7:0] report_data_rd;
reg [3:0] report_adress_rd; reg [3:0] report_adress_rd;
@ -59,119 +60,167 @@ module matrix_kbd ( input CLK, input RESET, input FREEZE, inout [15:0] ROWS, inp
reg report_wr_en; reg report_wr_en;
ram REPORT (CLK, report_wr_en, report_adress_wr, report_data_wr, report_adress_rd, report_data_rd); ram REPORT (CLK, report_wr_en, report_adress_wr, report_data_wr, report_adress_rd, report_data_rd);
ram RAM (CLK, ram_wr, ram_adr, temp, ram_adr, ram_rd);//module ram(input clk, wen, input [8:0] addr, input [7:0] wdata, output [7:0] rdata); ram RAM (CLK, last_wr, last_adr, COLUMN_SHADOW, last_adr, last_column);//module ram(input clk, wen, input [8:0] addr, input [7:0] wdata, output [7:0] rdata);
reg tmr_wr_en;
reg [7:0] tmr_to_ram;
wire [7:0] tmr_from_ram;
//reg [7:0] tmr_adr;
wire [6:0] tmr_adr;
//assign tmr_adr[6:3] = kbd_code;
assign tmr_adr [6:3] = row_counter;
//assign tmr_adr [2:0] = 0;
assign tmr_adr [2:0] = row_time[10:8]; //row_time[3:1];
ram CHATTERING_SUPRESSION_TIMERS (CLK, tmr_wr_en, tmr_adr, tmr_to_ram, tmr_adr, tmr_from_ram);
reg is_ghost;
always @ (negedge CLK) begin always @ (negedge CLK) begin
if (RESET == 0) begin if (RESET == 0) begin
//for (i = 0; i < 6; i = i + 1)
// report[i] = 0;
isr = 0; isr = 0;
isr_internal = 0; isr_internal = 0;
//init_delay_cnt = 0;
//init_ram_cnt = 0;
row_time = 0; row_time = 0;
row_counter = 0;
IS_RAM_INIT = 1; IS_RAM_INIT = 1;
ram_adr = 500; last_adr = 500;
report_adress_rd = 5; report_adress_rd = 5;
report_wr_en = 0; report_wr_en = 0;
//report_byte = 0; COLUMN_SHADOW = 255;
end end
else begin else begin
if (FREEZE == 0) begin if (FREEZE == 0) begin
/*if (REPORT_ADRESS == 0)
report_byte <= 10;
else if ((REPORT_ADRESS == 1) || (REPORT_ADRESS == 3))
report_byte <= 0;
else if (REPORT_ADRESS == 2)
report_byte <= report[0];
else
report_byte <= report[REPORT_ADRESS-3];*/
/*if (init_delay_cnt != 15)
init_delay_cnt = init_delay_cnt + 1;
else if (init_ram_cnt < 256) begin
ram_wr = 1;
ram_adr = init_ram_cnt;
temp = 255;
init_ram_cnt = init_ram_cnt + 1;
end*/
if (IS_RAM_INIT) begin if (IS_RAM_INIT) begin
ram_wr = 1; last_wr = 1;
ram_adr = ram_adr + 1; tmr_wr_en = 1;
temp = 255; last_adr = last_adr + 1;
COLUMN_SHADOW = 255;
tmr_to_ram = 0;
row_counter = last_adr[6:3];
row_time[10:8] = last_adr[2:0];
report_adress_rd = report_adress_rd + 1; report_adress_rd = report_adress_rd + 1;
if (report_adress_rd == 0) if (report_adress_rd == 0)
report_data_wr = 10; report_data_wr = 10;
else else
report_data_wr = 0;//report_adress_rd & 1; report_data_wr = 0;//report_adress_rd & 1;
report_wr_en = 1; report_wr_en = 1;
if (ram_adr == 130) begin if (last_adr == 130) begin
//ram_wr = 0; tmr_wr_en = 0;
last_wr = 0;
IS_RAM_INIT = 0; IS_RAM_INIT = 0;
report_wr_en = 0; report_wr_en = 0;
end end
end end
/*else if (init_ram_cnt == 256) begin
ram_wr = 0;
init_ram_cnt = init_ram_cnt + 1;
end*/
else begin else begin
row_time = row_time + 1; if (row_time == ONE_ROW_TIME) begin
if (row_time == 0) begin//== ONE_ROW_TIME) begin row_time = 0;
ram_wr = 0;
//row_time <= 0;
row_counter = row_counter + 1; row_counter = row_counter + 1;
ROWS_EN = 1 << row_counter; COLUMN_SHADOW <= COLUMNS; // LATCH STATE OF THE COLUMNS IN CURRENT ROW
ram_adr = row_counter; //last_adr = 0;
end
else begin
if (row_time == 0) begin//== ONE_ROW_TIME) begin
last_wr = 0;
ROWS_EN = 1 << ((row_counter+1) & 15);
last_adr = row_counter;
end
row_time = row_time + 1;
end end
// ROW 0 - D, 1 - A, 2 - C, 3 - B
/*if (row_time == (ROW_STT_PROCESS_TIME - 1)) begin
temp = ram_rd;
COLS_SHADOW <= COLUMNS;
end*/
//if (row_time == 8191/*(ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 7 + 1)*/)
// ram_wr = 1;
//if ((row_time[12:8] == 31) && (row_time[4:0] == 0)) begin if ((row_time[ONE_ROW_TIME_POW:11] == 0) && (row_time[7:0] < 140)) begin
if ((row_time[ONE_ROW_TIME_POW:8] == ((1<<(ONE_ROW_TIME_POW-7))-1)) && (row_time[4:0] == 0)) begin // if (COLUMN_SHADOW [row_time [10:8]] == 0) begin // START OF KEY PRESS PROCESSING
//temp = ram_rd; // if (row_time [7:0] == 0) // AT START OF EACH COLUMN PROCESS
//COLS_SHADOW = COLUMNS; // is_ghost = 0;
if (row_time[7:5] == 0) begin // end
temp = ram_rd; // else begin
COLS_SHADOW = COLUMNS; if (COLUMN_SHADOW [row_time [10:8]] == 0) begin
if (row_time [7] == 0) begin
is_ghost = 0;
end
else if (row_time [6:0] == 0)
last_adr = row_counter;
else if ((row_time [6:0] == 1) && (is_ghost == 0)) begin
// if (last_column[row_time[10:8]] == 1) begin
// is_pressed = 1;
// report_adress_rd = 2; // ADRESS TO MODIFIERS
// isr_internal = 1; // INTERNAL ISR AT NEXT TACT
// end
if (tmr_from_ram < CHATTERING_SUPRESSION_TIME)
tmr_to_ram = tmr_from_ram + 1;
else if (tmr_from_ram == CHATTERING_SUPRESSION_TIME) begin
isr_internal = 1;
is_pressed = 1;
report_adress_rd = 2;
tmr_to_ram = tmr_from_ram;
end
else
tmr_to_ram = tmr_from_ram;
end
end end
check_column (row_time[7:5]); else begin
if (row_time[7:5] == 7) last_adr = row_counter;
ram_wr = 1; tmr_to_ram = 0;
if (row_time [7:0] == 1) begin
if (last_column[row_time[10:8]] == 0) begin
isr_internal = 1;
is_pressed = 0;
report_adress_rd = 2;
end
end
end
// last_adr = row_counter;
// if (row_time[7:0] == 128) begin
// if (COLUMN_SHADOW[row_time[10:8]] != last_column[row_time[10:8]]) begin
// if ((COLUMN_SHADOW[row_time[10:8]] == 0) && (last_column[row_time[10:8]] == 1)) is_pressed = 1;
// else is_pressed = 0;
// isr_internal = 1; // INTERNAL ISR AT NEXT TACT
// report_adress_rd = 2; // ADRESS TO MODIFIERS
// end
// end
// if (row_time[7:0] == 130)
// tmr_wr_en = 1;
// else if (row_time[7:0] == 132)
// tmr_wr_en = 0;
//
// if (row_time[10:8] == 7) begin
// if (row_time[7:0] == 130)
// last_wr = 1;
// else if (row_time[7:0] == 132)
// last_wr = 0;
// end
end end
//else
// kbd_code = 255;
/*if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 0)) else if ((row_time[ONE_ROW_TIME_POW:11] == 0) && (row_time[7:0] == 250)) begin
check_column (0); tmr_wr_en = 1;
else if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 2)) if (row_time[10:8] == 7)
check_column (2); last_wr = 1;
else if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 1)) end
check_column (1);
else if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 3))
check_column (3);
else if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 4))
check_column (4);
else if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 5))
check_column (5);
else if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 6))
check_column (6);
else if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 7))
check_column (7);
else
kbd_code = 255;*/
// START PACK I2C_HID REPORT else if ((row_time[ONE_ROW_TIME_POW:11] == 0) && (row_time[7:0] == 252)) begin
tmr_wr_en = 0;
last_wr = 0;
end
// if ((row_time[ONE_ROW_TIME_POW:8] == 1/*((1<<(ONE_ROW_TIME_POW-7))-1)*/) && (row_time[4:0] == 0)) begin
// //if (row_time[7:5] == 0) begin
// // temp = last_column;
// //end
// check_column (row_time[7:5]);
// if (row_time[7:5] == 7)
// last_wr = 1;
// end
// START PACK I2C_HID REPORT
else if ((isr_internal == 1)/* && (row_time[4:0] > 1)*/) begin else if ((isr_internal == 1)/* && (row_time[4:0] > 1)*/) begin
if (report_wr_en == 1) begin if (report_wr_en == 1) begin
report_wr_en = 0; report_wr_en = 0;
isr_internal = 0; isr_internal = 0;
isr = 1; isr = 1;
if (is_pressed)
tmr_to_ram = tmr_to_ram + 1;
end end
else if (kbd_code_hid == 0) // IF KEY NOT EXIST, DO NOTHING else if (kbd_code_hid == 0) // IF KEY NOT EXIST, DO NOTHING
isr_internal = 0; isr_internal = 0;
@ -180,18 +229,24 @@ module matrix_kbd ( input CLK, input RESET, input FREEZE, inout [15:0] ROWS, inp
report_data_wr = report_data_rd | (1<<(kbd_code_hid & 8'h07)); report_data_wr = report_data_rd | (1<<(kbd_code_hid & 8'h07));
else else
report_data_wr = report_data_rd & (~(1<<(kbd_code_hid & 8'h07))); report_data_wr = report_data_rd & (~(1<<(kbd_code_hid & 8'h07)));
report_wr_en = 1; if (report_data_wr == report_data_rd) begin
isr_internal = 0;
if (is_pressed)
tmr_to_ram = tmr_to_ram + 1;
end
else
report_wr_en = 1;
end end
//else
// isr_internal = 0;
else if (report_adress_rd == 2) // IF BUTTON IS NOT MODIFIER, SET ADRESS TO FIRST BUTTON BYTE else if (report_adress_rd == 2) // IF BUTTON IS NOT MODIFIER, SET ADRESS TO FIRST BUTTON BYTE
report_adress_rd = 4; report_adress_rd = 4;
else if (report_adress_rd == 10) // IF TOO MUTCH ADRESSES SEEK, END ALG (BUTTONS ARE IN ADRESSES 4-9) else if (report_adress_rd == 10) // IF TOO MUTCH ADRESSES SEEK, END ALG (BUTTONS ARE IN ADRESSES 4-9)
isr_internal = 0; isr_internal = 0;
else begin else begin
if (is_pressed) begin if (is_pressed) begin
if (report_data_rd == kbd_code_hid) // IF BUTTON WITH SAME CODE IS IN REPORT if (report_data_rd == kbd_code_hid) begin // IF BUTTON WITH SAME CODE IS IN REPORT
isr_internal = 0; // CLEAR INTERNAL INTERRUPT, NO EXT INTERRUPT isr_internal = 0; // CLEAR INTERNAL INTERRUPT, NO EXT INTERRUPT
tmr_to_ram = tmr_to_ram + 1;
end
else if (report_data_rd == 0) begin // IF FREE ADRESS FOUND else if (report_data_rd == 0) begin // IF FREE ADRESS FOUND
report_data_wr = kbd_code_hid; // WRITE CODE TO THIS ADRESS report_data_wr = kbd_code_hid; // WRITE CODE TO THIS ADRESS
report_wr_en = 1; report_wr_en = 1;
@ -214,47 +269,7 @@ module matrix_kbd ( input CLK, input RESET, input FREEZE, inout [15:0] ROWS, inp
report_adress_rd = REPORT_ADRESS /*- 1*/; // IF REPORT FILLING PROCESS IS ENDED, SET ADRESS FROM TOP MODULE report_adress_rd = REPORT_ADRESS /*- 1*/; // IF REPORT FILLING PROCESS IS ENDED, SET ADRESS FROM TOP MODULE
isr <= 0; isr <= 0;
end end
/*if (kbd_code_hid != 0) begin
if (kbd_code_hid[7:3] == 5'b11100) begin
//if ((kbd_code_hid > 8'hDF) && (kbd_code_hid < 8'hE8)) begin
if (is_pressed)
report [0] = report [0] | (1<<(kbd_code_hid & 8'h07));
else
report [0] <= report [0] & (~(1<<(kbd_code_hid & 8'h07)));
isr = 1;
end
else begin
if (is_pressed) begin
isr = 1;
if (report [ 1 ] == 0)
report [ 1 ] <= kbd_code_hid;
else if (report [ 2 ] == 0)
report [ 2 ] <= kbd_code_hid;
else if (report [ 3 ] == 0)
report [ 3 ] <= kbd_code_hid;
else if (report [ 4 ] == 0)
report [ 4 ] <= kbd_code_hid;
else if (report [ 5 ] == 0)
report [ 5 ] <= kbd_code_hid;
else if (report [ 6 ] == 0)
report [ 6 ] <= kbd_code_hid;
else
isr = 0;
end
else begin
for (i = 1; i < 7; i = i + 1) begin
if (report [i] == kbd_code_hid) begin
//if (report [i] == kbd_code) begin
report [i] = 0;
isr = 1;
end
end
end
end
end // END OF KBD CODE SEND ALG
else
isr <= 0;*/
end end
end end
end end
@ -263,26 +278,18 @@ module matrix_kbd ( input CLK, input RESET, input FREEZE, inout [15:0] ROWS, inp
task check_column; task check_column;
input [2:0] column; input [2:0] column;
begin begin
if (COLS_SHADOW[column] != temp[column]) begin if (COLUMN_SHADOW[column] != last_column[column]) begin
//kbd_code = row_counter*8 + column; //kbd_code = row_counter*8 + column;
if ((COLS_SHADOW[column] == 0) && (temp[column] == 1)) is_pressed = 1; if ((COLUMN_SHADOW[column] == 0) && (last_column[column] == 1)) is_pressed = 1;
else is_pressed = 0; else is_pressed = 0;
isr_internal = 1; // INTERNAL ISR AT NEXT TACT isr_internal = 1; // INTERNAL ISR AT NEXT TACT
report_adress_rd = 2; // ADRESS TO MODIFIERS report_adress_rd = 2; // ADRESS TO MODIFIERS
end end
//else kbd_code = 255; //else kbd_code = 255;
temp[column] = COLS_SHADOW[column]; //temp[column] = COLUMN_SHADOW[column];
end end
endtask endtask
/*assign kbd_r0 = report[0];
assign kbd_r2 = report[1];
assign kbd_r3 = report[2];
assign kbd_r4 = report[3];
assign kbd_r5 = report[4];
assign kbd_r6 = report[5];
assign kbd_r7 = report[6];*/
//assign REPORT_DATA = report_byte;
assign INT = isr; assign INT = isr;
SB_RAM40_4K #( SB_RAM40_4K #(

47
i2c_keyboard/top.v
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@ -1,6 +1,6 @@
module top (input CLK, output LED1, LED2, LED3, LED4, LED5, module top (input CLK, output LED1, LED2, LED3, LED4, LED5,
input SCL, inout SDA, /*output ACK,*/ output INTERRUPT, //output INTERRUPT_INVERT, input SCL, inout SDA, /*output ACK,*/ output INTERRUPT,
input COM_RX, output COM_TX, COM_DCD, COM_DSR, COM_RTS, input COM_RX, output COM_TX, COM_DCD, COM_DSR, COM_RTS,
input [7:0] KBD_COLUMNS, inout [15:0] KBD_ROWS); input [7:0] KBD_COLUMNS, inout [15:0] KBD_ROWS);
@ -16,16 +16,12 @@ module top (input CLK, output LED1, LED2, LED3, LED4, LED5,
wire [7:0] I2C_TX_DESC; wire [7:0] I2C_TX_DESC;
wire [7:0] I2C_RX; // RECEIVED FROM MASTER wire [7:0] I2C_RX; // RECEIVED FROM MASTER
wire I2C_TRANS, I2C_READ, I2C_ACK, /*I2C_ACK_MSTR_CTRL,*/ I2C_WR; wire I2C_TRANS, I2C_READ, I2C_ACK, /*I2C_ACK_MSTR_CTRL,*/ I2C_WR;
//wire [7:0] I2C_COUNTER;
i2c_slave I2C (CLK, RESET, SCL, SDA, I2C_TRANS, I2C_READ, I2C_ACK, I2C_WR, //I2C_ACK_MSTR_CTRL, i2c_slave I2C (CLK, RESET, SCL, SDA, I2C_TRANS, I2C_READ, I2C_ACK, I2C_WR, //I2C_ACK_MSTR_CTRL,
I2C_RX, I2C_TX);//, I2C_COUNTER); I2C_RX, I2C_TX);//, I2C_COUNTER);
reg UART_WR, UART_DTR, UART_RTS, UART_DCD;//, UART_WR2; reg UART_WR, UART_DTR, UART_RTS, UART_DCD;//, UART_WR2;
reg [7:0] UART_TX_DATA; reg [7:0] UART_TX_DATA;
wire UART_ACTIVE, UART_TX_LINE; wire UART_ACTIVE, UART_TX_LINE;
/*initial begin
UART_WR = 0; UART_RTS = 1; UART_DTR = 0; UART_DCD = 0;
end*/
uart UART (CLK, RESET, UART_WR, UART_TX_DATA, UART_ACTIVE, UART_TX_LINE); uart UART (CLK, RESET, UART_WR, UART_TX_DATA, UART_ACTIVE, UART_TX_LINE);
//wire [7:0] kbd_report [6:0]; //wire [7:0] kbd_report [6:0];
@ -34,14 +30,14 @@ module top (input CLK, output LED1, LED2, LED3, LED4, LED5,
reg INT = 1; // INTERRUPT LINE TO HOST reg INT = 1; // INTERRUPT LINE TO HOST
reg [INTERRUPT_TMR_REFLESH:0] int_tmr; reg [INTERRUPT_TMR_REFLESH:0] int_tmr;
reg KBD_FREEZE = 1; // LOGIC REG FOR BLOCK KBD ACTIVITY WHEN I2C IS WORKING reg KBD_FREEZE = 1; // LOGIC REG FOR BLOCK KBD ACTIVITY WHEN I2C IS WORKING
matrix_kbd KEYBOARD (CLK, RESET, IS_RAM_INIT /*KBD_FREEZE*/, KBD_ROWS, KBD_COLUMNS, wr_cnt, report_data_wr, ISR);//kbd_report[0], kbd_report[1], kbd_report[2], kbd_report[3], kbd_report[4], kbd_report[5], kbd_report[6], ISR); wire KBD_DBG;
matrix_kbd KEYBOARD (CLK, RESET, IS_RAM_INIT /*KBD_FREEZE*/, KBD_ROWS, KBD_COLUMNS, wr_cnt, report_data_wr, ISR, KBD_DBG);//kbd_report[0], kbd_report[1], kbd_report[2], kbd_report[3], kbd_report[4], kbd_report[5], kbd_report[6], ISR);
descriptors I2C_HID_DESC (CLK, /*RESET, I2C_WR,*/ I2C_OUTPUT_TYPE[/*1:*/0], I2C_COUNTER, I2C_TX_DESC/*, kbd_report*/); descriptors I2C_HID_DESC ((1^CLK), /*RESET, I2C_WR,*/ I2C_OUTPUT_TYPE[/*1:*/0], I2C_COUNTER, I2C_TX_DESC/*, kbd_report*/);
reg [3:0] ring_wr, ring_rd; reg [3:0] ring_wr, ring_rd;
reg [3:0] wr_cnt; reg [3:0] wr_cnt;
reg report_wr_en; reg report_wr_en;
//reg [7:0] /*report_data_wadr,*/ /*report_data_radr,*/ //report_data_wr;
wire [7:0] report_data_radr, report_data_wadr, report_data_wr; wire [7:0] report_data_radr, report_data_wadr, report_data_wr;
assign report_data_radr[7:4] = ring_rd; assign report_data_radr[7:4] = ring_rd;
assign report_data_radr[3:0] = I2C_COUNTER; assign report_data_radr[3:0] = I2C_COUNTER;
@ -77,7 +73,6 @@ module top (input CLK, output LED1, LED2, LED3, LED4, LED5,
INT = 1; int_tmr = 0; INT = 1; int_tmr = 0;
ring_wr = 0; ring_rd = 15; wr_cnt = 0; ring_wr = 0; ring_rd = 15; wr_cnt = 0;
IS_RAM_INIT = 1; IS_RAM_INIT = 1;
//report_data_wadr = 245; // FIRST 10 TACTS ARE EMPTY
report_wr_en = 0; report_wr_en = 0;
end end
@ -85,9 +80,6 @@ module top (input CLK, output LED1, LED2, LED3, LED4, LED5,
else begin else begin
if (IS_RAM_INIT) begin if (IS_RAM_INIT) begin
//report_wr_en = 1;
//report_data_wadr = report_data_wadr + 1;
//report_data_wr = 0;
wr_cnt = wr_cnt + 1; wr_cnt = wr_cnt + 1;
if ((wr_cnt == 0) && (report_wr_en == 0)) if ((wr_cnt == 0) && (report_wr_en == 0))
report_wr_en = 1; report_wr_en = 1;
@ -95,10 +87,6 @@ module top (input CLK, output LED1, LED2, LED3, LED4, LED5,
report_wr_en = 0; report_wr_en = 0;
IS_RAM_INIT = 0; IS_RAM_INIT = 0;
end end
/*if (report_data_wadr == 17) begin
report_wr_en = 0;
IS_RAM_INIT = 0;
end*/
end end
else begin // START OF NON RESET AND NON INIT LOGIC else begin // START OF NON RESET AND NON INIT LOGIC
@ -109,12 +97,7 @@ module top (input CLK, output LED1, LED2, LED3, LED4, LED5,
if ((ring_wr + 1) != ring_rd) if ((ring_wr + 1) != ring_rd)
ring_wr = ring_wr + 1; ring_wr = ring_wr + 1;
report_wr_en = 1; report_wr_en = 1;
//report_data_wadr = ring_wr * 16 + 1;
//report_data_wr = 10;//kbd_report [0];
wr_cnt = 1; wr_cnt = 1;
//INT = 0;
//I2C_OUTPUT_TYPE = 2;//3;
//I2C_OUT_DESC_MASK = 8'h00;
end end
else if (wr_cnt != 0) begin // WRITING TO RAM REPORT FROM KEYBOARD else if (wr_cnt != 0) begin // WRITING TO RAM REPORT FROM KEYBOARD
@ -122,22 +105,14 @@ module top (input CLK, output LED1, LED2, LED3, LED4, LED5,
wr_cnt = 0; wr_cnt = 0;
report_wr_en = 0; report_wr_en = 0;
end end
else begin else
//report_data_wadr = ring_wr * 16 + wr_cnt + 1;
/*if ((wr_cnt == 1) || (wr_cnt == 3))
report_data_wr = 0;
else if (wr_cnt == 2)
report_data_wr = kbd_report [wr_cnt - 2];
else
report_data_wr = kbd_report [wr_cnt - 3];*/
wr_cnt = wr_cnt + 1; wr_cnt = wr_cnt + 1;
end
end end
// ---------------------------- I2C NEW BYTE TX/RX RISING/FALLING EDGE, RISING - ALL LOGIC, FALLING - UART TX -------------- // // ---------------------------- I2C NEW BYTE TX/RX RISING/FALLING EDGE, RISING - ALL LOGIC, FALLING - UART TX -------------- //
if ((last_wr == 0) && (I2C_WR == 1)) begin // I2C NEW BYTE TX/RX if ((last_wr == 0) && (I2C_WR == 1)) begin // I2C NEW BYTE TX/RX
//I2C_COUNTER = I2C_COUNTER - 1;
if (I2C_READ == 0) begin // I2C_FROM_HOST if (I2C_READ == 0) begin // I2C_FROM_HOST
if (I2C_COUNTER == 0) begin if (I2C_COUNTER == 0) begin
@ -182,10 +157,7 @@ module top (input CLK, output LED1, LED2, LED3, LED4, LED5,
if (I2C_COUNTER == 0) begin if (I2C_COUNTER == 0) begin
if (ring_rd != ring_wr) if (ring_rd != ring_wr)
ring_rd = ring_rd + 1; ring_rd = ring_rd + 1;
//report_data_radr = ring_rd * 10;
end end
//else
// report_data_radr = report_data_radr + 1;
end end
end end
UART_WR <= 0; UART_WR <= 0;
@ -212,7 +184,6 @@ module top (input CLK, output LED1, LED2, LED3, LED4, LED5,
end // I2C_START_CONDITION (UART FF) - END end // I2C_START_CONDITION (UART FF) - END
else if ((last_trans == 1) && (I2C_TRANS == 0)) begin // I2C_STOP CONDITION (OR REPEAT START DETECTED) else if ((last_trans == 1) && (I2C_TRANS == 0)) begin // I2C_STOP CONDITION (OR REPEAT START DETECTED)
//KBD_FREEZE <= 0;
if (I2C_READ == 0) begin // DECODING PACKET RECEIVED FROM HOST if (I2C_READ == 0) begin // DECODING PACKET RECEIVED FROM HOST
if (((i2c_input_data_type < 4) && (I2C_COUNTER != 2)) || ((i2c_input_data_type == 4) && (I2C_COUNTER != 5)) || ((i2c_input_data_type == 5) && (I2C_COUNTER != 4)) || ((i2c_input_data_type == 6) && (I2C_COUNTER != 6)) || ((i2c_input_data_type == 7) && (I2C_COUNTER != 9))) if (((i2c_input_data_type < 4) && (I2C_COUNTER != 2)) || ((i2c_input_data_type == 4) && (I2C_COUNTER != 5)) || ((i2c_input_data_type == 5) && (I2C_COUNTER != 4)) || ((i2c_input_data_type == 6) && (I2C_COUNTER != 6)) || ((i2c_input_data_type == 7) && (I2C_COUNTER != 9)))
i2c_input_data_type = 0; i2c_input_data_type = 0;
@ -241,7 +212,6 @@ module top (input CLK, output LED1, LED2, LED3, LED4, LED5,
I2C_OUT_DESC_MASK = 0; I2C_OUT_DESC_MASK = 0;
end end
UART_WR <= 0; UART_WR <= 0;
//last_trans = I2C_TRANS;
end // I2C_STOP CONDITION (OR REPEAT START DETECTED) - END end // I2C_STOP CONDITION (OR REPEAT START DETECTED) - END
// ---------------- INTERRUPT TO HOST GENERATING LOGIC: DELAY AND INTERRUPT GENERATING (IF NEED) --------------- // // ---------------- INTERRUPT TO HOST GENERATING LOGIC: DELAY AND INTERRUPT GENERATING (IF NEED) --------------- //
@ -260,22 +230,21 @@ module top (input CLK, output LED1, LED2, LED3, LED4, LED5,
last_isr <= ISR; last_isr <= ISR;
end // END OF NON RESET AND NON INIT LOGIC end // END OF NON RESET AND NON INIT LOGIC
end end
end end
assign LED5 = I2C_TRANS; assign LED5 = I2C_TRANS;
//assign LED5 = COM_RX; //assign LED5 = COM_RX;
assign LED1 = INT ^ 1;//KBD_COLUMNS[0];//I2C_OUTPUT_TYPE[0];//I2C_RX[0]; assign LED1 = INT ^ 1;//KBD_COLUMNS[0];//I2C_OUTPUT_TYPE[0];//I2C_RX[0];
//assign INTERRUPT_INVERT = INT ^ 1;
//assign LED2 = I2C_OUTPUT_TYPE[0]; //assign LED2 = I2C_OUTPUT_TYPE[0];
//assign LED3 = I2C_OUTPUT_TYPE[1]; //assign LED3 = I2C_OUTPUT_TYPE[1];
assign LED2 = KBD_LED_STATUS[0]; //assign LED2 = KBD_LED_STATUS[0];
assign LED3 = KBD_LED_STATUS[1]; assign LED3 = KBD_LED_STATUS[1];
assign LED4 = KBD_LED_STATUS[2];//KBD_FREEZE;//UART_ACTIVE; assign LED4 = KBD_LED_STATUS[2];//KBD_FREEZE;//UART_ACTIVE;
//assign LED3 = UART_ACTIVE; //assign LED3 = UART_ACTIVE;
//assign LED4 = uart_double_ff; //assign LED4 = uart_double_ff;
//assign ACK = I2C_READ;//I2C_WR; //I2C_ACK; //assign ACK = I2C_READ;//I2C_WR; //I2C_ACK;
assign LED2 = KBD_DBG;
assign COM_TX = UART_TX_LINE;//COM_RX; assign COM_TX = UART_TX_LINE;//COM_RX;
assign INTERRUPT = INT; assign INTERRUPT = INT;

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