davor
|
050a70079a
|
move one audio-v pin from bank0 to bank7 so
now all audio jack pins are on bank7
|
7 years ago |
|
davor
|
0d71e508ae
|
analog: audio ring2 resistor DAC network connected to FPGA
copper infill is getting thin, so minimal-thickness traces
are used 0.127 mm
|
7 years ago |
|
Emard
|
ba4c8e8d22
|
PCB v1.6 SDRAM fully reworked
|
7 years ago |
|
davor
|
bc4b88ee58
|
Micro SD: using SCHD3A0100
|
7 years ago |
|
davor
|
f3d84dbfdc
|
LED D19 was oriented wrong, now correct
|
7 years ago |
|
Emard
|
bab7ee607e
|
placeholder for 1.5k pullup for usb 1.0
|
7 years ago |
|
Emard
|
9cc436ce8c
|
Additional VCC 2.2uF blocking capacitors near the switching
power supply to form PI-filter with another 2.2uF near BGA
|
7 years ago |
|
davor
|
0229a768ad
|
FPGA direct-to-pin Hackish USB transciver 27 ohm + 3.6 V zener
|
7 years ago |
|
davor
|
fdf38ad9a1
|
DIP switch moved to the right, near RAM.
Maybe should be moved more to the right not to overlap with OLED
|
7 years ago |
|
davor
|
5f589c33f4
|
USB directly to FPGA for possible USB1.1 core
|
7 years ago |
|
davor
|
236f63488a
|
DIP SWITCH routed
|
7 years ago |
|
davor
|
32836831ae
|
i2c of RTC connected to GPDI i2c
|
7 years ago |
|
davor
|
2153a220a0
|
schematic symbol for ADC MAX11123
small PCB traces cleanup
ADC chip placed on PCB but connected only to GND
|
7 years ago |
|
davor
|
81b3ea5da0
|
adding minimal set of 3 2.2uF capacitor for 1.2V, 2.5V and 3.3V
|
8 years ago |
|
Emard
|
ee7d266543
|
Resistors for LEDs
|
8 years ago |
|
Emard
|
18aef04f2c
|
JTAG header
|
8 years ago |
|
davor
|
b7500cc477
|
increasing thickness of power traces, moving clock
to a bank which is always at 3.3V
|
8 years ago |
|
davor
|
1a122bfc67
|
fully routed
|
8 years ago |
|
davor
|
dbf4b92a22
|
audio DAC routed
|
8 years ago |
|
davor
|
23b588ff16
|
Routing... 4 routes remaining
|
8 years ago |
|
Emard
|
28c4106026
|
J2 GPIO: routed in the purple plane only
|
8 years ago |
|
Emard
|
4c13f262e8
|
connecting FTDI TXD/RXD
|
8 years ago |
|
Emard
|
092e601af1
|
connecting LEDs
|
8 years ago |
|
Emard
|
364957f9e0
|
connecting OLED
|
8 years ago |
|
Emard
|
feb31c8f87
|
moving inner layer routes away from BGA
|
8 years ago |
|
Emard
|
e30bbeea40
|
routing 4 GPIO on J2
|
8 years ago |
|
Emard
|
48dc148919
|
manually routing J1 differential
|
8 years ago |
|
Davor
|
3446afcc08
|
optimizing PCB component placement
and audio bit ordering
|
8 years ago |
|
Davor
|
19b884baef
|
using corrected schem symbol, reordering pins
|
8 years ago |
|
Davor
|
39dce76f0a
|
use new schem symbol
|
8 years ago |
|
Davor
|
2cda80c3a8
|
manually routed few tracks of GPIO
|
8 years ago |
|
davor
|
70fb21781b
|
reorder GPDI differential pairs for almost straitforward routing
|
8 years ago |
|
davor
|
a8f1214b27
|
reorder SDRAM to FPGA connection for straightforward routing
|
8 years ago |
|
Davor
|
aef3945a8e
|
differential pin naming for GPDI, USB, GPIO
|
8 years ago |
|
Davor
|
ec42a18d26
|
reordering RAM connections to use peripheral pins near SDRAM chip
|
8 years ago |
|
davor
|
d6fd30e59c
|
jumper to disable wifi module
|
8 years ago |
|
davor
|
9570c1137b
|
small edits
|
8 years ago |
|
davor
|
c297a5294f
|
adding 25 MHz oscillator and moving some parts around
|
8 years ago |
|
Davor
|
a477fbd050
|
connecting flash config chip
|
8 years ago |
|
davor
|
dc1ae11172
|
partially routed board using "freeroute" autorouter
|
8 years ago |
|
davor
|
85cb0b3f93
|
Placing 40-pin connectors side-by-side,
changing ft2232 to ft231x
|
8 years ago |
|
davor
|
a7de1a4e58
|
power button
|
8 years ago |
|
davor
|
5d5a4031cc
|
pins VREF named on schematic symbol of fpga
|
8 years ago |
|
davor
|
a60712b2f6
|
place renumbered schematic units of the fpga chip
|
8 years ago |
|
davor
|
e2899667ef
|
place all available banks to gpio page
|
8 years ago |
|
davor
|
c3889467a0
|
rename gpio pins same as BGA pin e.g. A9, C11, ...
|
8 years ago |
|
davor
|
4f3fabdb5f
|
oled updated on the schematic and PCB
|
8 years ago |
|
davor
|
6639abded3
|
add 4 mounting holes
|
8 years ago |
|
davor
|
b661cacede
|
Change to 2x20 pin headers, PCB layout currently sub-optimal
|
8 years ago |
|
davor
|
f7185a0ff7
|
improving wifi SD and JTAG pinouts.
Unsure of JTAG (GPIO20 is NC on ESP-32S module?)
|
8 years ago |
