Davor
|
39dce76f0a
|
use new schem symbol
|
8 years ago |
|
Davor
|
e5f97e1897
|
schematic symbol FPGA: mark bank physical location
on the floorplan
|
8 years ago |
|
Davor
|
2cda80c3a8
|
manually routed few tracks of GPIO
|
8 years ago |
|
Davor
|
8a53acb71a
|
cleaning GPDI routes and moving OLED back in place
|
8 years ago |
|
davor
|
70fb21781b
|
reorder GPDI differential pairs for almost straitforward routing
|
8 years ago |
|
davor
|
4a26254f9a
|
correcting schematic symbol of FPGA
|
8 years ago |
|
davor
|
a8f1214b27
|
reorder SDRAM to FPGA connection for straightforward routing
|
8 years ago |
|
davor
|
01d1cad2ec
|
add missing pins in schematic symbol for BANK3
|
8 years ago |
|
Davor
|
19c91e5c6b
|
differential pair track thickness and spacing
|
8 years ago |
|
Davor
|
632e5bd443
|
importing netlist with differential pairs named + -
|
8 years ago |
|
Davor
|
aef3945a8e
|
differential pin naming for GPDI, USB, GPIO
|
8 years ago |
|
Davor
|
d0791b1e47
|
correcting few pin numbering errors in FPGA schematic symbols
|
8 years ago |
|
Davor
|
ec42a18d26
|
reordering RAM connections to use peripheral pins near SDRAM chip
|
8 years ago |
|
Davor
|
40aef19979
|
FPGA schematic symbol add mssing PR41A, PR41B to BANK3
|
8 years ago |
|
davor
|
53f11a6950
|
reducing track width to 0.19 mm to pass out of 2nd row of BGA
|
8 years ago |
|
Davor
|
961755fc98
|
manual routing BGA power
|
8 years ago |
|
Davor
|
af042dfef0
|
manually routing BGA power
|
8 years ago |
|
davor
|
a1d25d9d24
|
create copper fill layers
|
8 years ago |
|
davor
|
d6fd30e59c
|
jumper to disable wifi module
|
8 years ago |
|
davor
|
38517df9f6
|
fine tuning via diameters and clearances
|
8 years ago |
|
davor
|
dd597e7b49
|
board production rules for oshpart
|
8 years ago |
|
davor
|
1c5b8a64a3
|
use new footprint for crystal oscillator
|
8 years ago |
|
davor
|
75e4f9b564
|
correct footprint for crystal oscillator 25 MHz
|
8 years ago |
|
davor
|
508318d712
|
PCB moving 3.5mm DAC resistors below 3.5m jack, side-by-side
|
8 years ago |
|
davor
|
e9825a4105
|
enlarging the board for 7x2.54 mm to fit triple protoboard
moving OLED into the center (but display turned upside down)
moving heavy parts GPDI and 3.5mm jack on top side
better rearranging the buttons
|
8 years ago |
|
davor
|
0af487f23c
|
renaming clocks
|
8 years ago |
|
davor
|
9570c1137b
|
small edits
|
8 years ago |
|
davor
|
c297a5294f
|
adding 25 MHz oscillator and moving some parts around
|
8 years ago |
|
Davor
|
f894f386df
|
design rules, move to BGA netlist to route with thinner traces
|
8 years ago |
|
Davor
|
12e89e677a
|
connecting wifi, usbserial, oled, sd card
|
8 years ago |
|
Davor
|
0ca9b4cb0e
|
notify possible extra width of the board 7x2.54 mm
that would fit into protoboard
|
8 years ago |
|
Davor
|
3e68526ccb
|
it acutally routed but schematic is still incomplete :)
After freeroute overnight run, DRC complained only for
tracks too close to holes or vias and that is easy to
manually fix
|
8 years ago |
|
Davor
|
498701d2b4
|
gitignore intermediate files of freeroute
|
8 years ago |
|
Davor
|
4a63816ba2
|
remove freeroute intermediate file
|
8 years ago |
|
Davor
|
ad0ae760b5
|
overnight run of freeroute routed much
but couldn't route it all
|
8 years ago |
|
Davor
|
a477fbd050
|
connecting flash config chip
|
8 years ago |
|
davor
|
a8c293805f
|
moving battery down,
partially routed
|
8 years ago |
|
davor
|
dc1ae11172
|
partially routed board using "freeroute" autorouter
|
8 years ago |
|
davor
|
e37f17e390
|
moving PCB components around
|
8 years ago |
|
davor
|
2dedab2d9a
|
moving 8-pin chip away from 3.5mm jack
|
8 years ago |
|
davor
|
9b02f3265d
|
compacting the board to hold 2.54mm headers, buttons moved
randomly just to fit
|
8 years ago |
|
davor
|
85cb0b3f93
|
Placing 40-pin connectors side-by-side,
changing ft2232 to ft231x
|
8 years ago |
|
davor
|
5221d8270a
|
add footprint for several ftdi usbserial chip
including FT231X
|
8 years ago |
|
davor
|
2de9717740
|
fpga bga schematic symbol set exact chip name
|
8 years ago |
|
davor
|
a7de1a4e58
|
power button
|
8 years ago |
|
davor
|
5d5a4031cc
|
pins VREF named on schematic symbol of fpga
|
8 years ago |
|
davor
|
a60712b2f6
|
place renumbered schematic units of the fpga chip
|
8 years ago |
|
davor
|
067962ec48
|
fpga schematic symbol: renumbering bank units
|
8 years ago |
|
davor
|
e2899667ef
|
place all available banks to gpio page
|
8 years ago |
|
davor
|
4d31d658fb
|
Added pins for remaining banks.
Need to verify if everything is correct.
|
8 years ago |
