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i2c_keyboard update

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master
Ivan Olenichev 7 years ago
parent 61f1fd3bd4
commit e0d61dc647
14 changed files with 17393 additions and 24080 deletions
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i2c_keyboard/.sconsign.dblite
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i2c_keyboard/Makefile
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@ -17,3 +17,5 @@ nextpnr: top.v inouts.pcf
clean: clean:
rm -f i2c_kbd_alt.blif i2c_kbd_alt.asc i2c_kbd_alt.ex i2c_kbd_alt.bin i2_kbd_alt.json rm -f i2c_kbd_alt.blif i2c_kbd_alt.asc i2c_kbd_alt.ex i2c_kbd_alt.bin i2_kbd_alt.json
#icetime -tmd hx1k i2c_kbd_alt.asc

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i2c_keyboard/README
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@ -16,3 +16,10 @@ Need to install (sudo apt-get update and sudo apt-get install):
qtcreator qtcreator
libqt5serialport5 libqt5serialport5
libqt5serialport5-dev libqt5serialport5-dev
Used tools (place&route):
1. Apio, version 0.4.0
2. Arachne-pnr 0.1+325+0 (git sha1 840bdfd, g++ 5.4.0-6ubuntu1~16.04.10 -O2)
3. nextpnr-ice40 -- Next Generation Place and Route (git sha1 8bda861)
In some commits will be information about occupied LCs (with using each place&route tool).

64
i2c_keyboard/descriptors.v
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@ -1,27 +1,31 @@
module descriptors (input CLK, input RESET, input RD_REQUEST, input [1:0] DESC_TYPE, input [7:0] ADR, output /*reg*/ [7:0] VAL/*, input [63:0] kbd_report*/); module descriptors (input CLK, /*input RESET, input RD_REQUEST,*/ input /*[1:0]*/ DESC_TYPE, input [6:0] ADR, output /*reg*/ [7:0] VAL/*, input [63:0] kbd_report*/);
parameter HID_REPORT_DESC_LEN = 63; parameter HID_REPORT_DESC_LEN = 63;
wire [7:0] RAM_ADR;
assign RAM_ADR[6:0] = ADR[6:0];
assign RAM_ADR[7] = DESC_TYPE;
//reg [(8*30-1):0] i2c_hid_desc;// = 'h_1E_00__00_01__46_00__02_00__03_00__0A_00__04_00__03_00__05_00__06_00__9F_04__01_01__00_01__00_00_00_00; //reg [(8*30-1):0] i2c_hid_desc;// = 'h_1E_00__00_01__46_00__02_00__03_00__0A_00__04_00__03_00__05_00__06_00__9F_04__01_01__00_01__00_00_00_00;
//reg [(8*HID_REPORT_DESC_LEN-1):0] hid_report_desc; //reg [(8*HID_REPORT_DESC_LEN-1):0] hid_report_desc;
parameter READ_ADRESS_OFFSET = 2; //parameter READ_ADRESS_OFFSET = 2;
reg last_rd_request = 0; //reg last_rd_request = 0;
reg tx_flag = 0; // AT POSEDGE OF RD_REQUEST DATA FROM RAM MOVES TO RAM_RD_REG, AT NEXT CLK DATA MUST BE WRITE TO VAL //reg tx_flag = 0; // AT POSEDGE OF RD_REQUEST DATA FROM RAM MOVES TO RAM_RD_REG, AT NEXT CLK DATA MUST BE WRITE TO VAL
reg [7:0] real_adress; //reg [6:0] real_adress;
//reg [7:0] ram_rd_t1; //reg [7:0] ram_rd_t1;
//reg [7:0] ram_rd_t2; //reg [7:0] ram_rd_t2;
always @ (posedge CLK) begin //always @ (posedge CLK) begin
if (RESET == 0) begin //if (RESET == 0) begin
//i2c_hid_desc <= 'h_1E_00__00_01__50_00__02_00__03_00__0A_00__04_00__03_00__05_00__06_00__9F_04__01_01__00_01__00_00_00_00; //i2c_hid_desc <= 'h_1E_00__00_01__50_00__02_00__03_00__0A_00__04_00__03_00__05_00__06_00__9F_04__01_01__00_01__00_00_00_00;
//hid_report_desc <= 'h__05_01__09_06__A1_01__05_07__85_01___19_E0__29_E7__15_00__25_01__75_01__95_08__81_02___95_01__75_08__81_01___95_05__75_01__05_05__85_01__19_01__29_05__91_02___95_01__75_03__91_03___95_06__75_08__15_00__25_65__05_07__19_00__29_65__81_00__C0; //hid_report_desc <= 'h__05_01__09_06__A1_01__05_07__85_01___19_E0__29_E7__15_00__25_01__75_01__95_08__81_02___95_01__75_08__81_01___95_05__75_01__05_05__85_01__19_01__29_05__91_02___95_01__75_03__91_03___95_06__75_08__15_00__25_65__05_07__19_00__29_65__81_00__C0;
//i2c_hid_desc [207:200] <= HID_REPORT_DESC_LEN[7:0]; //i2c_hid_desc [207:200] <= HID_REPORT_DESC_LEN[7:0];
//i2c_hid_desc [199:192] <= HID_REPORT_DESC_LEN[15:8]; //i2c_hid_desc [199:192] <= HID_REPORT_DESC_LEN[15:8];
last_rd_request <= 0; // last_rd_request <= 0;
real_adress = 0; // real_adress = 0;
end //end
else begin // else begin
/*if (tx_flag == 1) begin // NEXT CLK AFTER POSEDGE REQUEST /*if (tx_flag == 1) begin // NEXT CLK AFTER POSEDGE REQUEST
if (DESC_TYPE == 1) if (DESC_TYPE == 1)
VAL <= ram_rd_t1; VAL <= ram_rd_t1;
@ -29,13 +33,13 @@ always @ (posedge CLK) begin
VAL <= ram_rd_t2; VAL <= ram_rd_t2;
tx_flag = 0;*/ tx_flag = 0;*/
//end //end
if ((last_rd_request == 0) && (RD_REQUEST == 1)) begin // if ((last_rd_request == 0) && (RD_REQUEST == 1)) begin
if (DESC_TYPE == 1) // if (DESC_TYPE == 1)
real_adress = ADR; // real_adress = ADR;
else // else
real_adress = ADR + 32; // real_adress = ADR + 32;
//if (DESC_TYPE == 1) begin //if (DESC_TYPE == 1) begin
tx_flag = 1; // WAIT NEXT CLK // tx_flag = 1; // WAIT NEXT CLK
/* case (ADR) 2: VAL <= 8'h1E; 3: VAL <= 0; // 2-3 - DESCR LEN (30), /* case (ADR) 2: VAL <= 8'h1E; 3: VAL <= 0; // 2-3 - DESCR LEN (30),
4: VAL <= 0; 5: VAL <= 1; // 4-5 - bcdVersion 4: VAL <= 0; 5: VAL <= 1; // 4-5 - bcdVersion
6: VAL <= HID_REPORT_DESC_LEN[7:0]; 7: VAL <= HID_REPORT_DESC_LEN[15:8]; 6: VAL <= HID_REPORT_DESC_LEN[7:0]; 7: VAL <= HID_REPORT_DESC_LEN[15:8];
@ -119,10 +123,10 @@ always @ (posedge CLK) begin
else else
VAL <= kbd_report[ (8 * (10 - READ_ADRESS + READ_ADRESS_OFFSET - 1) + 7) : (8 * (10 - READ_ADRESS + READ_ADRESS_OFFSET - 1) + 0) ]; VAL <= kbd_report[ (8 * (10 - READ_ADRESS + READ_ADRESS_OFFSET - 1) + 7) : (8 * (10 - READ_ADRESS + READ_ADRESS_OFFSET - 1) + 0) ];
end*/ end*/
end // end
last_rd_request <= RD_REQUEST; // last_rd_request <= RD_REQUEST;
end // end
end //end
/* 2: VAL <= 8'h1E; 3: VAL <= 0; // 2-3 - DESCR LEN (30), /* 2: VAL <= 8'h1E; 3: VAL <= 0; // 2-3 - DESCR LEN (30),
4: VAL <= 0; 5: VAL <= 1; // 4-5 - bcdVersion 4: VAL <= 0; 5: VAL <= 1; // 4-5 - bcdVersion
@ -141,18 +145,20 @@ end
*/ */
SB_RAM40_4K #( SB_RAM40_4K #(
.INIT_0(256'h0000_0004__0000_000A__0000_0003__0000_0002__0000_003F__0001_0000__0000_001E___0000_0000), /*.INIT_0(256'h0000_0004__0000_000A__0000_0003__0000_0002__0000_003F__0001_0000__0000_001E___0000_0000),
.INIT_1(256'h0000_0000__0000_0000__0001_0000__0001_0001__0004_009F__0000_0006__0000_0005___0000_0003), .INIT_1(256'h0000_0000__0000_0000__0001_0000__0001_0001__0004_009F__0000_0006__0000_0005___0000_0003),*/
.INIT_2(256'h0000_0015__00E7_0029__00E0_0019__0007_0005__0001_00A1__0006_0009__0001_0005___0000_0000), .INIT_0(256'h0003__0000_0004__0000_000A__0000_0003__0000_0002__0000_003F__0001_0000__0000_001E___0000),
.INIT_3(256'h0005_0095__0001_0081__0008_0075__0001_0095__0002_0081__0008_0095__0001_0075___0001_0025), .INIT_1(256'h0000__0000_0000__0000_0000__0001_0000__0001_0001__0004_009F__0000_0006__0000_0005___0000),
.INIT_4(256'h0003_0091__0003_0075__0001_0095__0002_0091__0005_0029__0001_0019__0008_0005___0001_0075), .INIT_8(256'h0025__0000_0015__00E7_0029__00E0_0019__0007_0005__0001_00A1__0006_0009__0001_0005___0000),
.INIT_5(256'h0000_0081__0065_0029__0000_0019__0007_0005__0065_0025__0000_0015__0008_0075___0006_0095), .INIT_9(256'h0075__0005_0095__0001_0081__0008_0075__0001_0095__0002_0081__0008_0095__0001_0075___0001),
.INIT_6(256'h0000_0000__0000_0000__0000_0000__0000_0000__0000_0000__0000_0000__0000_0000___0000_00C0), .INIT_A(256'h0095__0003_0091__0003_0075__0001_0095__0002_0091__0005_0029__0001_0019__0008_0005___0001),
.INIT_B(256'h00C0__0000_0081__0065_0029__0000_0019__0007_0005__0065_0025__0000_0015__0008_0075___0006),
.INIT_C(256'h0000__0000_0000__0000_0000__0000_0000__0000_0000__0000_0000__0000_0000__0000_0000___0000),
.WRITE_MODE(1), .WRITE_MODE(1),
.READ_MODE(1) .READ_MODE(1)
) descriptors ( ) descriptors (
.RDATA(VAL), .RDATA(VAL),
.RADDR(real_adress), .RADDR(RAM_ADR/*real_adress*/),
.RCLK(CLK), .RCLK(CLK),
.RCLKE(1'b1), .RCLKE(1'b1),
.RE(1'b1), .RE(1'b1),

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i2c_keyboard/hardware.asc
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i2c_keyboard/hardware.bin
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i2c_keyboard/hardware.blif
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i2c_keyboard/i2c_kbd_alt.bin
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i2c_keyboard/i2c_kbd_alt.blif
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i2c_keyboard/i2c_kbd_alt.ex
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i2c_keyboard/i2c_slave.v
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@ -1,8 +1,8 @@
module i2c_slave (input CLK, input RESET, module i2c_slave (input CLK, input RESET,
input SCL, inout SDA, input SCL, inout SDA,
output IS_TRANSMISSION, output IS_READ, output IS_ACK, output WR, //output ACK_MASTER_CTRL, output IS_TRANSMISSION, output IS_READ, output IS_ACK, output WR, //output ACK_MASTER_CTRL,
output [7:0] RECEIVED_BYTE, input [7:0] BYTE_TO_TRANSMIT, output [7:0] RECEIVED_BYTE, input [7:0] BYTE_TO_TRANSMIT);//,
output [(MAX_I2C_TRANSACTION_EXP2-1):0] COUNTER); //output [(MAX_I2C_TRANSACTION_EXP2-1):0] COUNTER);
// ALL OPERATIONS WITH MEMORY ARE IN POSEDGE CLK, IN NEGEDGE - ONLY SCL AND SDA LATCH // ALL OPERATIONS WITH MEMORY ARE IN POSEDGE CLK, IN NEGEDGE - ONLY SCL AND SDA LATCH
// COUNTER = 0 - ADRESS RECEIVED, COUNTER >=1 - DATA TRANSMISSION // COUNTER = 0 - ADRESS RECEIVED, COUNTER >=1 - DATA TRANSMISSION
// RECEIVED BYTES MUST READ WHEN WR POSEDGE, ADRESS NOT READING ###AND BYTE COUNTER >=1 (BYTE COUNTER = 0 - ADRESS) // RECEIVED BYTES MUST READ WHEN WR POSEDGE, ADRESS NOT READING ###AND BYTE COUNTER >=1 (BYTE COUNTER = 0 - ADRESS)
@ -11,7 +11,7 @@ module i2c_slave (input CLK, input RESET,
// LAST BYTE HAS NO WR ####BUT LAST BYTE NOT TRANSMITTED (BECAUSE MASTER STOPS TRANSMIT) // LAST BYTE HAS NO WR ####BUT LAST BYTE NOT TRANSMITTED (BECAUSE MASTER STOPS TRANSMIT)
parameter I2C_ADRESS = 7'h34; parameter I2C_ADRESS = 7'h34;
parameter MAX_I2C_TRANSACTION_EXP2 = 8; // !!! - FOR LIMIT BYTES TO TX/RX (WITH ADRESS) //parameter MAX_I2C_TRANSACTION_EXP2 = 8; // !!! - FOR LIMIT BYTES TO TX/RX (WITH ADRESS)
reg /*SDA_IN,*/ SDA_DIR, SDA_OUT; reg /*SDA_IN,*/ SDA_DIR, SDA_OUT;
wire SDA_IN; wire SDA_IN;
@ -33,10 +33,10 @@ module i2c_slave (input CLK, input RESET,
reg [3:0] i2c_bit_counter; reg [3:0] i2c_bit_counter;
reg [7:0] received_byte; reg [7:0] received_byte;
reg [7:0] byte_to_transmit; reg [7:0] byte_to_transmit;
reg [(MAX_I2C_TRANSACTION_EXP2-1):0] byte_counter; //reg [(MAX_I2C_TRANSACTION_EXP2-1):0] byte_counter;
//reg is_for_me; reg is_adress;
reg is_ack; reg is_ack;
reg wr;//reg ack_master_ctrl; reg wr;
// FILTER // FILTER
reg SCLF, SDAF; reg SCLF, SDAF;
@ -45,54 +45,29 @@ module i2c_slave (input CLK, input RESET,
simple_filter FLT_SCL (CLK, RESET, SCLF, SCLD); simple_filter FLT_SCL (CLK, RESET, SCLF, SCLD);
simple_filter FLT_SDA (CLK, RESET, SDAF, SDAD); simple_filter FLT_SDA (CLK, RESET, SDAF, SDAD);
always@(negedge CLK) begin always@(posedge CLK) begin
SCLF <= SCL; SCLF = SCL;
SDAF <= SDA_IN; SDAF = SDA_IN;
end end
always@(posedge CLK or negedge RESET) begin always@(negedge CLK/* or negedge RESET*/) begin
if (RESET == 0) if (RESET == 0)
i2c_state_machine <= 0; i2c_state_machine = 0;
else begin
/* if (scl_cnt != 0) begin
scl_cnt = scl_cnt - 1;
if (scl_cnt == 0) begin
if (SCLD != SCLF)
SCLD = SCLF;
end
end
else begin
if (SCLD != SCLF)
scl_cnt = 3'd7;
end
if (sda_cnt != 0) begin
sda_cnt = sda_cnt - 1;
if (sda_cnt == 0) begin
if (SDAD != SDAF)
SDAD = SDAF;
end
end
else begin else begin
if (SDAD != SDAF)
sda_cnt = 3'd7;
end*/
// END OF FILTER
//SDA_IN = SDA; // FOR IVERILOG //SDA_IN = SDA; // FOR IVERILOG
if ((SDAD == 0) && (SDA_LAST == 1) && (SCLD == 1)) begin if ((SDAD == 0) && (SDA_LAST == 1) && (SCLD == 1)) begin
i2c_state_machine = 1; i2c_state_machine = 1;
i2c_start_latency = 0; i2c_start_latency = 0;
i2c_bit_counter = 4'd8; i2c_bit_counter = 4'd8;
byte_counter = 9'd0; is_adress = 1;//byte_counter = 9'd0;
//is_for_me = 1; // RESETS TO ZERO WHEN ADRESS CHECKING
SDA_DIR = 0; SDA_DIR = 0;
is_ack = 0; is_ack = 0;
//ack_master_ctrl = 1;
wr = 0; wr = 0;
is_read = 0;
end end
else if ((i2c_state_machine == 1) && (i2c_start_latency == 0)) begin else if ((i2c_state_machine == 1) && (i2c_start_latency == 0)) begin
i2c_start_latency = 1; i2c_start_latency = 1;
is_read = 0;
end end
if ((SDAD == 1) && (SDA_LAST == 0) && (SCLD == 1)) begin if ((SDAD == 1) && (SDA_LAST == 0) && (SCLD == 1)) begin
i2c_state_machine = 0; i2c_state_machine = 0;
@ -109,24 +84,29 @@ module i2c_slave (input CLK, input RESET,
end end
else begin else begin
if ((SCL_LAST == 1) && (SCLD == 0) && (is_ack == 0)) begin if ((SCL_LAST == 1) && (SCLD == 0) && (is_ack == 0)) begin
if (byte_counter == 0) begin if (is_adress == 1) begin
if (received_byte[7:1] != I2C_ADRESS) if (received_byte[7:1] != I2C_ADRESS)
i2c_state_machine = 0; //is_for_me = 0; i2c_state_machine = 0; //is_for_me = 0;
is_read = received_byte[0]; is_read = received_byte[0];
//is_adress = 0;
end end
else begin //else begin
// EMIT SIGNAL OF BYTE RECEIVING // EMIT SIGNAL OF BYTE RECEIVING
end //end
if (byte_counter != ((1<<MAX_I2C_TRANSACTION_EXP2) - 1)) //if (byte_counter != ((1<<MAX_I2C_TRANSACTION_EXP2) - 1))
byte_counter = byte_counter + 1; // byte_counter = byte_counter + 1;
SDA_DIR = i2c_state_machine; //is_for_me; SDA_DIR = i2c_state_machine; //is_for_me;
is_ack = i2c_state_machine; //1; is_ack = i2c_state_machine; //1;
//if (is_read) begin //if (is_read) begin
// i2c_bit_counter = 8; // i2c_bit_counter = 8;
//end //end
end end
else if ((SCL_LAST == 0) && (SCLD == 1) && (is_ack == 1) && (byte_counter > 1)) else if ((SCL_LAST == 0) && (SCLD == 1) && (is_ack == 1)) begin//(byte_counter > 1))
if (is_adress == 1)
is_adress = 0;
else
wr = 1; wr = 1;
end
else if ((SCL_LAST == 1) && (SCLD == 0) && (is_ack == 1)) begin else if ((SCL_LAST == 1) && (SCLD == 0) && (is_ack == 1)) begin
is_ack = 0; is_ack = 0;
SDA_DIR = 0; SDA_DIR = 0;
@ -153,8 +133,8 @@ module i2c_slave (input CLK, input RESET,
i2c_bit_counter = 8; i2c_bit_counter = 8;
i2c_state_machine = (SDAD ^ 1) | SDA_DIR; //ack_master_ctrl = SDAD+1; // MAYBE TRANSMIT BYTE REPEAT i2c_state_machine = (SDAD ^ 1) | SDA_DIR; //ack_master_ctrl = SDAD+1; // MAYBE TRANSMIT BYTE REPEAT
wr = (SDAD ^ 1) | SDA_DIR; wr = (SDAD ^ 1) | SDA_DIR;
if (byte_counter != ((1<<MAX_I2C_TRANSACTION_EXP2) - 1)) //if (byte_counter != ((1<<MAX_I2C_TRANSACTION_EXP2) - 1))
byte_counter = byte_counter + 1; // byte_counter = byte_counter + 1;
// EMIT SIGNAL OF BYTE TO TRANSMIT // EMIT SIGNAL OF BYTE TO TRANSMIT
end end
end end
@ -173,7 +153,7 @@ module i2c_slave (input CLK, input RESET,
assign WR = wr;//assign ACK_MASTER_CTRL = ack_master_ctrl; assign WR = wr;//assign ACK_MASTER_CTRL = ack_master_ctrl;
assign RECEIVED_BYTE = received_byte; assign RECEIVED_BYTE = received_byte;
//assign BYTE_TO_TRANSMIT = byte_to_transmit; //assign BYTE_TO_TRANSMIT = byte_to_transmit;
assign COUNTER = byte_counter; //assign COUNTER = byte_counter;
SB_IO #( SB_IO #(
.PIN_TYPE(6'b 1010_01), .PIN_TYPE(6'b 1010_01),

147
i2c_keyboard/matrix_kbd.v
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@ -1,4 +1,6 @@
module matrix_kbd (input CLK, input RESET, input FREEZE, inout [15:0] ROWS, input [7:0] COLUMNS, output [7:0] kbd_r0, kbd_r2, kbd_r3, kbd_r4, kbd_r5, kbd_r6, kbd_r7, output INT); module matrix_kbd ( input CLK, input RESET, input FREEZE, inout [15:0] ROWS, input [7:0] COLUMNS,
input [3:0] REPORT_ADRESS, output [7:0] REPORT_DATA, output INT);
//output [7:0] kbd_r0, kbd_r2, kbd_r3, kbd_r4, kbd_r5, kbd_r6, kbd_r7, output INT);
// * - ESC (29), 7 - F1 (3A), 4 - F2 (3B), 1 - NUM_LOCK (53) // * - ESC (29), 7 - F1 (3A), 4 - F2 (3B), 1 - NUM_LOCK (53)
// 0 - CAPS LOCK (39), 8 - R (15), 5 - BACKSPACE (2A), 2 - ENTER (58) // 0 - CAPS LOCK (39), 8 - R (15), 5 - BACKSPACE (2A), 2 - ENTER (58)
@ -8,27 +10,32 @@ module matrix_kbd (input CLK, input RESET, input FREEZE, inout [15:0] ROWS, inpu
parameter ONE_ROW_TIME = 8000; parameter ONE_ROW_TIME = 8000;
parameter ROW_STT_PROCESS_TIME = 7000; parameter ROW_STT_PROCESS_TIME = 7000;
parameter ONE_COLUMN_PROCESS_TIME = 50; parameter ONE_COLUMN_PROCESS_TIME = 50;
parameter ONE_ROW_TIME_POW = 12; // 15 - 65536 tacts or 5.46 ms, 14 - 32768 tacts or 2.73 ms, 13 - 16384 tacts or 1.36 ms, parameter ONE_ROW_TIME_POW = 14; // 15 - 65536 tacts or 5.46 ms, 14 - 32768 tacts or 2.73 ms, 13 - 16384 tacts or 1.36 ms,
// 12 - 8191 tacts or 683 mks, 11 - 4096 tacts or 341 mks, 10 - 2048 tacts or 171 ms, 9 - 1024 tacts or 85 mks, 8 - 512 tacts or 43 ms, // 12 - 8191 tacts or 683 mks, 11 - 4096 tacts or 341 mks, 10 - 2048 tacts or 171 mks, 9 - 1024 tacts or 85 mks, 8 - 512 tacts or 43 mks,
// 7 - 256 tacts or 21 mks, other values have no guaranties // 7 - 256 tacts or 21 mks, other values have no guaranties
parameter ONE_CALC_TIME_POW = 4; // 3 - 16 tacts or 1.3 mks, 4 - 32 tacts or 2.7 mks, 5 - 64 tacts or 5.3 mks, 6 - 128 tacts or 10.7 mks parameter ONE_CALC_TIME_POW = 4; // 3 - 16 tacts or 1.3 mks, 4 - 32 tacts or 2.7 mks, 5 - 64 tacts or 5.3 mks, 6 - 128 tacts or 10.7 mks
// ONE_ROW_TIME_POW > (ONE_CALC_TIME_POW - 3); ONE_CALC_TIME_POW > 2 (if 2 or smaller, top module overrun may occur) // ONE_ROW_TIME_POW > (ONE_CALC_TIME_POW - 3); ONE_CALC_TIME_POW > 2 (if 2 or smaller, top module overrun may occur)
reg [12:0] row_time = 0; reg [ONE_ROW_TIME_POW:0] row_time = 0;
reg [3:0] row_counter; reg [3:0] row_counter;
reg [7:0] temp; reg [7:0] temp;
reg [7:0] i; reg [7:0] i;
reg [7:0] report [6:0]; // NO BYTE 2 //reg [7:0] report [6:0]; // NO BYTE 2
//reg [7:0] report_byte;
reg isr; reg isr;
reg isr_internal;
reg [15:0] ROWS_EN = 0; reg [15:0] ROWS_EN = 0;
reg [15:0] ROWS_OUT = 0; reg [15:0] ROWS_OUT = 0;
wire [15:0] ROWS_IN; wire [15:0] ROWS_IN;
reg [7:0] COLS_SHADOW; reg [7:0] COLS_SHADOW;
reg [7:0] kbd_code; //reg [7:0] kbd_code;
wire [6:0] kbd_code;
assign kbd_code [2:0] = row_time[7:5]; // COLUMN NUM
assign kbd_code [6:3] = row_counter; // ROW NUM
wire [7:0] kbd_code_hid; wire [7:0] kbd_code_hid;
reg is_pressed; reg is_pressed;
@ -36,33 +43,72 @@ module matrix_kbd (input CLK, input RESET, input FREEZE, inout [15:0] ROWS, inpu
reg [8:0] ram_adr; reg [8:0] ram_adr;
wire [7:0] ram_rd; wire [7:0] ram_rd;
reg [3:0] init_delay_cnt; //reg [3:0] init_delay_cnt;
reg [8:0] init_ram_cnt; //reg [8:0] init_ram_cnt;
reg IS_RAM_INIT = 0;
/*always @ (negedge CLK) begin /*always @ (negedge CLK) begin
COLS_SHADOW <= COLUMNS; COLS_SHADOW <= COLUMNS;
end*/ end*/
wire [7:0] report_data_rd;
reg [3:0] report_adress_rd;
reg [7:0] report_data_wr;
wire [3:0] report_adress_wr;
assign report_adress_wr = report_adress_rd;
assign REPORT_DATA = report_data_rd;
reg report_wr_en;
ram REPORT (CLK, report_wr_en, report_adress_wr, report_data_wr, report_adress_rd, report_data_rd);
ram RAM (CLK, ram_wr, ram_adr, temp, ram_adr, ram_rd);//module ram(input clk, wen, input [8:0] addr, input [7:0] wdata, output [7:0] rdata); ram RAM (CLK, ram_wr, ram_adr, temp, ram_adr, ram_rd);//module ram(input clk, wen, input [8:0] addr, input [7:0] wdata, output [7:0] rdata);
always @ (posedge CLK) begin always @ (negedge CLK) begin
if (RESET == 0) begin if (RESET == 0) begin
for (i = 0; i < 6; i = i + 1) //for (i = 0; i < 6; i = i + 1)
report[i] = 0; // report[i] = 0;
isr = 0; isr = 0;
init_delay_cnt = 0; isr_internal = 0;
init_ram_cnt = 0; //init_delay_cnt = 0;
//init_ram_cnt = 0;
row_time = 0; row_time = 0;
IS_RAM_INIT = 1;
ram_adr = 500;
report_adress_rd = 5;
report_wr_en = 0;
//report_byte = 0;
end end
else begin else begin
if (FREEZE == 0) begin if (FREEZE == 0) begin
if (init_delay_cnt != 15) /*if (REPORT_ADRESS == 0)
report_byte <= 10;
else if ((REPORT_ADRESS == 1) || (REPORT_ADRESS == 3))
report_byte <= 0;
else if (REPORT_ADRESS == 2)
report_byte <= report[0];
else
report_byte <= report[REPORT_ADRESS-3];*/
/*if (init_delay_cnt != 15)
init_delay_cnt = init_delay_cnt + 1; init_delay_cnt = init_delay_cnt + 1;
else if (init_ram_cnt < 256) begin else if (init_ram_cnt < 256) begin
ram_wr = 1; ram_wr = 1;
ram_adr = init_ram_cnt; ram_adr = init_ram_cnt;
temp = 255; temp = 255;
init_ram_cnt = init_ram_cnt + 1; init_ram_cnt = init_ram_cnt + 1;
end*/
if (IS_RAM_INIT) begin
ram_wr = 1;
ram_adr = ram_adr + 1;
temp = 255;
report_adress_rd = report_adress_rd + 1;
if (report_adress_rd == 0)
report_data_wr = 10;
else
report_data_wr = 0;//report_adress_rd & 1;
report_wr_en = 1;
if (ram_adr == 130) begin
//ram_wr = 0;
IS_RAM_INIT = 0;
report_wr_en = 0;
end
end end
/*else if (init_ram_cnt == 256) begin /*else if (init_ram_cnt == 256) begin
ram_wr = 0; ram_wr = 0;
@ -85,7 +131,8 @@ module matrix_kbd (input CLK, input RESET, input FREEZE, inout [15:0] ROWS, inpu
//if (row_time == 8191/*(ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 7 + 1)*/) //if (row_time == 8191/*(ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 7 + 1)*/)
// ram_wr = 1; // ram_wr = 1;
if ((row_time[12:8] == 31) && (row_time[4:0] == 0)) begin //if ((row_time[12:8] == 31) && (row_time[4:0] == 0)) begin
if ((row_time[ONE_ROW_TIME_POW:8] == ((1<<(ONE_ROW_TIME_POW-7))-1)) && (row_time[4:0] == 0)) begin
//temp = ram_rd; //temp = ram_rd;
//COLS_SHADOW = COLUMNS; //COLS_SHADOW = COLUMNS;
if (row_time[7:5] == 0) begin if (row_time[7:5] == 0) begin
@ -96,8 +143,8 @@ module matrix_kbd (input CLK, input RESET, input FREEZE, inout [15:0] ROWS, inpu
if (row_time[7:5] == 7) if (row_time[7:5] == 7)
ram_wr = 1; ram_wr = 1;
end end
else //else
kbd_code = 255; // kbd_code = 255;
/*if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 0)) /*if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 0))
check_column (0); check_column (0);
@ -119,7 +166,55 @@ module matrix_kbd (input CLK, input RESET, input FREEZE, inout [15:0] ROWS, inpu
kbd_code = 255;*/ kbd_code = 255;*/
// START PACK I2C_HID REPORT // START PACK I2C_HID REPORT
if (kbd_code_hid != 0) begin
else if ((isr_internal == 1)/* && (row_time[4:0] > 1)*/) begin
if (report_wr_en == 1) begin
report_wr_en = 0;
isr_internal = 0;
isr = 1;
end
else if (kbd_code_hid == 0) // IF KEY NOT EXIST, DO NOTHING
isr_internal = 0;
else if (kbd_code_hid[7:3] == 5'b11100) begin // BYTE WITH MODIFIERS IS READ AT START OF ALG
if (is_pressed)
report_data_wr = report_data_rd | (1<<(kbd_code_hid & 8'h07));
else
report_data_wr = report_data_rd & (~(1<<(kbd_code_hid & 8'h07)));
report_wr_en = 1;
end
//else
// isr_internal = 0;
else if (report_adress_rd == 2) // IF BUTTON IS NOT MODIFIER, SET ADRESS TO FIRST BUTTON BYTE
report_adress_rd = 4;
else if (report_adress_rd == 10) // IF TOO MUTCH ADRESSES SEEK, END ALG (BUTTONS ARE IN ADRESSES 4-9)
isr_internal = 0;
else begin
if (is_pressed) begin
if (report_data_rd == kbd_code_hid) // IF BUTTON WITH SAME CODE IS IN REPORT
isr_internal = 0; // CLEAR INTERNAL INTERRUPT, NO EXT INTERRUPT
else if (report_data_rd == 0) begin // IF FREE ADRESS FOUND
report_data_wr = kbd_code_hid; // WRITE CODE TO THIS ADRESS
report_wr_en = 1;
end
else
report_adress_rd = report_adress_rd + 1; // IF NO FREE PLACE, CONTINUE SEEK
end
else begin // BUTTON RELEASED
if (report_data_rd == kbd_code_hid) begin // IF ADRESS WITH THIS CODE FOUND
report_data_wr = 0; // WRITE 0 TO THIS ADRESS (BTN RELEASED)
report_wr_en = 1;
end
else
report_adress_rd = report_adress_rd + 1; // IF THIS CODE NOT FOUND, CONTINUE SEEK
end
end
end
else begin// if (isr_internal == 0) begin
report_adress_rd = REPORT_ADRESS /*- 1*/; // IF REPORT FILLING PROCESS IS ENDED, SET ADRESS FROM TOP MODULE
isr <= 0;
end
/*if (kbd_code_hid != 0) begin
if (kbd_code_hid[7:3] == 5'b11100) begin if (kbd_code_hid[7:3] == 5'b11100) begin
//if ((kbd_code_hid > 8'hDF) && (kbd_code_hid < 8'hE8)) begin //if ((kbd_code_hid > 8'hDF) && (kbd_code_hid < 8'hE8)) begin
if (is_pressed) if (is_pressed)
@ -149,7 +244,8 @@ module matrix_kbd (input CLK, input RESET, input FREEZE, inout [15:0] ROWS, inpu
else begin else begin
for (i = 1; i < 7; i = i + 1) begin for (i = 1; i < 7; i = i + 1) begin
if (report [i] == kbd_code_hid/*kbd_code*/) begin if (report [i] == kbd_code_hid) begin
//if (report [i] == kbd_code) begin
report [i] = 0; report [i] = 0;
isr = 1; isr = 1;
end end
@ -158,7 +254,7 @@ module matrix_kbd (input CLK, input RESET, input FREEZE, inout [15:0] ROWS, inpu
end end
end // END OF KBD CODE SEND ALG end // END OF KBD CODE SEND ALG
else else
isr <= 0; isr <= 0;*/
end end
end end
end end
@ -168,22 +264,25 @@ module matrix_kbd (input CLK, input RESET, input FREEZE, inout [15:0] ROWS, inpu
input [2:0] column; input [2:0] column;
begin begin
if (COLS_SHADOW[column] != temp[column]) begin if (COLS_SHADOW[column] != temp[column]) begin
kbd_code = row_counter*8 + column; //kbd_code = row_counter*8 + column;
if ((COLS_SHADOW[column] == 0) && (temp[column] == 1)) is_pressed = 1; if ((COLS_SHADOW[column] == 0) && (temp[column] == 1)) is_pressed = 1;
else is_pressed = 0; else is_pressed = 0;
isr_internal = 1; // INTERNAL ISR AT NEXT TACT
report_adress_rd = 2; // ADRESS TO MODIFIERS
end end
else kbd_code = 255; //else kbd_code = 255;
temp[column] = COLS_SHADOW[column]; temp[column] = COLS_SHADOW[column];
end end
endtask endtask
assign kbd_r0 = report[0]; /*assign kbd_r0 = report[0];
assign kbd_r2 = report[1]; assign kbd_r2 = report[1];
assign kbd_r3 = report[2]; assign kbd_r3 = report[2];
assign kbd_r4 = report[3]; assign kbd_r4 = report[3];
assign kbd_r5 = report[4]; assign kbd_r5 = report[4];
assign kbd_r6 = report[5]; assign kbd_r6 = report[5];
assign kbd_r7 = report[6]; assign kbd_r7 = report[6];*/
//assign REPORT_DATA = report_byte;
assign INT = isr; assign INT = isr;
SB_RAM40_4K #( SB_RAM40_4K #(

230
i2c_keyboard/top.v
Unescape View File

@ -4,6 +4,7 @@ module top (input CLK, output LED1, LED2, LED3, LED4, LED5,
input COM_RX, output COM_TX, COM_DCD, COM_DSR, COM_RTS, input COM_RX, output COM_TX, COM_DCD, COM_DSR, COM_RTS,
input [7:0] KBD_COLUMNS, inout [15:0] KBD_ROWS); input [7:0] KBD_COLUMNS, inout [15:0] KBD_ROWS);
parameter INTERRUPT_TMR_REFLESH = 14; // 14 - 2^14=16384 tacts or 1.37 ms, 19 - 2^19=524288 tacts or 43.7 ms, 23 - 2^23=8388608 tacts or 0.7 s parameter INTERRUPT_TMR_REFLESH = 14; // 14 - 2^14=16384 tacts or 1.37 ms, 19 - 2^19=524288 tacts or 43.7 ms, 23 - 2^23=8388608 tacts or 0.7 s
// 23 - 1119 LCs, 14 - 1081 LCs (in commit 1b6fc60221b595c2a0f69509d29b6e5c3110feb0) // 23 - 1119 LCs, 14 - 1081 LCs (in commit 1b6fc60221b595c2a0f69509d29b6e5c3110feb0)
@ -11,195 +12,185 @@ module top (input CLK, output LED1, LED2, LED3, LED4, LED5,
reg [3:0] rststate = 0; reg [3:0] rststate = 0;
assign RESET = &rststate; assign RESET = &rststate;
//reg [7:0] I2C_TX; // TRANSMITTED TO MASTER
wire [7:0] I2C_TX; wire [7:0] I2C_TX;
reg [7:0] I2C_TX_DESC; wire [7:0] I2C_TX_DESC;
//reg [7:0] I2C_TX_REPORT;
wire [7:0] I2C_RX; // RECEIVED FROM MASTER wire [7:0] I2C_RX; // RECEIVED FROM MASTER
wire I2C_TRANS, I2C_READ, I2C_ACK, I2C_ACK_MSTR_CTRL, I2C_WR; wire I2C_TRANS, I2C_READ, I2C_ACK, /*I2C_ACK_MSTR_CTRL,*/ I2C_WR;
wire [7:0] I2C_COUNTER; //wire [7:0] I2C_COUNTER;
i2c_slave I2C (CLK, RESET, SCL, SDA, I2C_TRANS, I2C_READ, I2C_ACK, I2C_WR, //I2C_ACK_MSTR_CTRL, i2c_slave I2C (CLK, RESET, SCL, SDA, I2C_TRANS, I2C_READ, I2C_ACK, I2C_WR, //I2C_ACK_MSTR_CTRL,
I2C_RX, I2C_TX, I2C_COUNTER); I2C_RX, I2C_TX);//, I2C_COUNTER);
reg UART_WR, UART_DTR, UART_RTS, UART_DCD; reg UART_WR, UART_DTR, UART_RTS, UART_DCD;//, UART_WR2;
reg [7:0] UART_TX_DATA; reg [7:0] UART_TX_DATA;
wire UART_ACTIVE, UART_TX_LINE; wire UART_ACTIVE, UART_TX_LINE;
initial begin /*initial begin
UART_WR = 0; UART_RTS = 1; UART_DTR = 0; UART_DCD = 0; UART_WR = 0; UART_RTS = 1; UART_DTR = 0; UART_DCD = 0;
end end*/
uart UART (CLK, RESET, UART_WR, UART_TX_DATA, UART_ACTIVE, UART_TX_LINE); uart UART (CLK, RESET, UART_WR, UART_TX_DATA, UART_ACTIVE, UART_TX_LINE);
//wire [63:0] kbd_report; //wire [7:0] kbd_report [6:0];
wire [7:0] kbd_report [6:0]; wire [7:0] report_byte;
wire ISR; wire ISR;
reg INT = 1; // INTERRUPT LINE TO HOST reg INT = 1; // INTERRUPT LINE TO HOST
reg [INTERRUPT_TMR_REFLESH:0] int_tmr; reg [INTERRUPT_TMR_REFLESH:0] int_tmr;
reg KBD_FREEZE = 1; // LOGIC REG FOR BLOCK KBD ACTIVITY WHEN I2C IS WORKING reg KBD_FREEZE = 1; // LOGIC REG FOR BLOCK KBD ACTIVITY WHEN I2C IS WORKING
//reg IS_EMPTY_REPORT = 0; // REGISTER FOR CORRECT START (HOST MUST REQUEST EMPTY REGISTER AFTER INTERRUPT. THEN INTERRRUPT SET TO 1) matrix_kbd KEYBOARD (CLK, RESET, IS_RAM_INIT /*KBD_FREEZE*/, KBD_ROWS, KBD_COLUMNS, wr_cnt, report_data_wr, ISR);//kbd_report[0], kbd_report[1], kbd_report[2], kbd_report[3], kbd_report[4], kbd_report[5], kbd_report[6], ISR);
matrix_kbd KEYBOARD (CLK, RESET, 0 /*KBD_FREEZE*/, KBD_ROWS, KBD_COLUMNS, kbd_report[0], kbd_report[1], kbd_report[2], kbd_report[3], kbd_report[4], kbd_report[5], kbd_report[6], ISR);
descriptors I2C_HID_DESC (CLK, RESET, I2C_WR, I2C_OUTPUT_TYPE[1:0], I2C_COUNTER, I2C_TX_DESC/*, kbd_report*/); descriptors I2C_HID_DESC (CLK, /*RESET, I2C_WR,*/ I2C_OUTPUT_TYPE[/*1:*/0], I2C_COUNTER, I2C_TX_DESC/*, kbd_report*/);
//reg [7:0] ring_report [(8*8-1):0];
reg [7:0] init_ram_cnt;
reg [3:0] ring_wr, ring_rd; reg [3:0] ring_wr, ring_rd;
reg [3:0] wr_cnt; reg [3:0] wr_cnt;
reg report_wr_en; reg report_wr_en;
reg [7:0] report_data_wadr, report_data_radr, report_data_wr; //reg [7:0] /*report_data_wadr,*/ /*report_data_radr,*/ //report_data_wr;
wire [7:0] report_data_radr, report_data_wadr, report_data_wr;
assign report_data_radr[7:4] = ring_rd;
assign report_data_radr[3:0] = I2C_COUNTER;
assign report_data_wadr[7:4] = ring_wr;
assign report_data_wadr[3:0] = wr_cnt;
wire [7:0] report_data_rd; wire [7:0] report_data_rd;
ram REPORT_DATA (CLK, report_wr_en, report_data_wadr, report_data_wr, report_data_radr, report_data_rd); ram REPORT_DATA ((1^CLK), report_wr_en, report_data_wadr, report_data_wr, report_data_radr, report_data_rd);
assign I2C_TX = (I2C_TX_DESC & I2C_OUT_DESC_MASK) | (/*I2C_TX_REPORT*/report_data_rd & (~I2C_OUT_DESC_MASK)); assign I2C_TX = (I2C_TX_DESC & I2C_OUT_DESC_MASK) | (/*I2C_TX_REPORT*/report_data_rd & (~I2C_OUT_DESC_MASK));
//parameter MAX_INPUT_LEN = 10; reg [2:0] temp_output_report;
//reg [7:0] I2C_INPUT_DATA [MAX_INPUT_LEN:0];
reg [7:0] temp_output_report;
reg [3:0] i2c_input_data_type; // 0 - UNKNOWN, 1 - I2C_HID_DESC_REQUEST, 2 - HID_REPORT_DESC_REQUEST, 3 - INPUT_REPORT_REQUEST, 4 - OUTPUT_REPORT_SET reg [3:0] i2c_input_data_type; // 0 - UNKNOWN, 1 - I2C_HID_DESC_REQUEST, 2 - HID_REPORT_DESC_REQUEST, 3 - INPUT_REPORT_REQUEST, 4 - OUTPUT_REPORT_SET
// 5 - RESET, 6 - GET_INPUT_REPORT, 7 - SET_OUTPUT_REPORT // 5 - RESET, 6 - GET_INPUT_REPORT, 7 - SET_OUTPUT_REPORT
reg [7:0] I2C_INPUT_LEN = 0; reg [/*7*/6:0] I2C_COUNTER = 0;
reg [2:0] I2C_OUTPUT_TYPE = 0; // 0 - ALL ZERO DATA, 1 - I2C HID DESCR, 2 - OUTPUT REPORT, 3 - HID REPORT DESCR reg [2:0] I2C_OUTPUT_TYPE = 0; // 0 - I2C HID DESCR, 1 - HID REPORT DESC, 2 - INPUT REPORT
reg [7:0] I2C_OUT_DESC_MASK = 0; reg [7:0] I2C_OUT_DESC_MASK = 0;
reg [7:0] KBD_LED_STATUS = 0; reg [2:0] KBD_LED_STATUS = 0;
reg last_wr = 0, last_trans = 0, last_isr = 0;
reg last_wr = 0, last_trans = 0, last_uart_active = 0, last_isr = 0, uart_double_ff = 0; reg IS_RAM_INIT = 0;
always @(posedge CLK) begin always @(posedge CLK) begin
// RESET LOGIC // RESET LOGIC
rststate <= rststate + !RESET; rststate <= rststate + !RESET;
if (RESET == 0) begin if (RESET == 0) begin
I2C_OUTPUT_TYPE = 3;//0; I2C_OUTPUT_TYPE = 2;//3;//0;
I2C_OUT_DESC_MASK = 0; I2C_OUT_DESC_MASK = 0;
KBD_LED_STATUS = 5; // BIT 0 - NUM LOCK, BIT 1 - CAPS LOCK, BIT 2 - SCROOL LOCK
uart_double_ff = 0; last_trans = 0; last_uart_active = 0; last_isr = 0;
I2C_INPUT_LEN = 0;
INT = 1; int_tmr = 0;
UART_WR = 0; UART_WR = 0;
KBD_LED_STATUS = 0; // BIT 0 - NUM LOCK, BIT 1 - CAPS LOCK, BIT 2 - SCROOL LOCK
last_trans = 0; last_isr = 0; last_wr = 0;
I2C_COUNTER = 0;
INT = 1; int_tmr = 0;
ring_wr = 0; ring_rd = 15; wr_cnt = 0; ring_wr = 0; ring_rd = 15; wr_cnt = 0;
init_ram_cnt = 0; IS_RAM_INIT = 1;
//report_data_wadr = 245; // FIRST 10 TACTS ARE EMPTY
report_wr_en = 0;
end end
// NOT RESET MODE LOGIC // NOT RESET MODE LOGIC
else begin else begin
if (init_ram_cnt < 170) begin
if (IS_RAM_INIT) begin
//report_wr_en = 1;
//report_data_wadr = report_data_wadr + 1;
//report_data_wr = 0;
wr_cnt = wr_cnt + 1;
if ((wr_cnt == 0) && (report_wr_en == 0))
report_wr_en = 1; report_wr_en = 1;
if (init_ram_cnt < 10) else if ((wr_cnt == 0) && (report_wr_en == 1)) begin
report_data_wadr = 0; report_wr_en = 0;
else IS_RAM_INIT = 0;
report_data_wadr = init_ram_cnt - 10;
report_data_wr = 0;//report_data_adr + 1;
init_ram_cnt = init_ram_cnt + 1;
end end
else if (init_ram_cnt == 170) begin /*if (report_data_wadr == 17) begin
report_wr_en = 0; report_wr_en = 0;
init_ram_cnt = init_ram_cnt + 1; IS_RAM_INIT = 0;
end*/
end end
else if ((last_isr == 0) && (ISR == 1)/* && (INT == 1)*/) begin // INTERRUPT FROM KEYBOARD else begin // START OF NON RESET AND NON INIT LOGIC
// ------------------------- KBD INTERRUPT ------------------------ //
if ((last_isr == 1/*0*/) && (ISR == 0/*1*/)) begin // INTERRUPT FROM KEYBOARD
if ((ring_wr + 1) != ring_rd) if ((ring_wr + 1) != ring_rd)
ring_wr = ring_wr + 1; ring_wr = ring_wr + 1;
report_wr_en = 1; report_wr_en = 1;
report_data_wadr = ring_wr * 10; //report_data_wadr = ring_wr * 16 + 1;
report_data_wr = 10;//kbd_report [0]; //report_data_wr = 10;//kbd_report [0];
wr_cnt = 1; wr_cnt = 1;
INT = 0; //INT = 0;
I2C_OUTPUT_TYPE = 3; //I2C_OUTPUT_TYPE = 2;//3;
I2C_OUT_DESC_MASK = 8'h00; //I2C_OUT_DESC_MASK = 8'h00;
last_isr = ISR;
end end
else if ((last_isr == 1) && (ISR == 0))
last_isr = ISR;
else if (wr_cnt != 0) begin else if (wr_cnt != 0) begin // WRITING TO RAM REPORT FROM KEYBOARD
if (wr_cnt == 10) begin if (wr_cnt == 11) begin
wr_cnt = 0; wr_cnt = 0;
report_wr_en = 0; report_wr_en = 0;
end end
else begin else begin
report_data_wadr = ring_wr * 10 + wr_cnt; //report_data_wadr = ring_wr * 16 + wr_cnt + 1;
if ((wr_cnt == 1) || (wr_cnt == 3)) /*if ((wr_cnt == 1) || (wr_cnt == 3))
report_data_wr = 0; report_data_wr = 0;
else if (wr_cnt == 2) else if (wr_cnt == 2)
report_data_wr = kbd_report [wr_cnt - 2]; report_data_wr = kbd_report [wr_cnt - 2];
else else
report_data_wr = kbd_report [wr_cnt - 3]; report_data_wr = kbd_report [wr_cnt - 3];*/
wr_cnt = wr_cnt + 1; wr_cnt = wr_cnt + 1;
end end
end end
else if ((last_wr == 0) && (I2C_WR == 1)) begin // I2C NEW BYTE TX/RX // ---------------------------- I2C NEW BYTE TX/RX RISING/FALLING EDGE, RISING - ALL LOGIC, FALLING - UART TX -------------- //
I2C_INPUT_LEN = I2C_COUNTER - 1;
if ((last_wr == 0) && (I2C_WR == 1)) begin // I2C NEW BYTE TX/RX
//I2C_COUNTER = I2C_COUNTER - 1;
if (I2C_READ == 0) begin // I2C_FROM_HOST if (I2C_READ == 0) begin // I2C_FROM_HOST
if (I2C_COUNTER == 2) begin if (I2C_COUNTER == 0) begin
if ((I2C_RX > 5) || (I2C_RX < 1)) if ((I2C_RX > 5) || (I2C_RX < 1))
i2c_input_data_type = 0; i2c_input_data_type = 0;
else else
i2c_input_data_type = I2C_RX; i2c_input_data_type = I2C_RX;
end end
else if (I2C_COUNTER == 3) begin else if (I2C_COUNTER == 1) begin
if (I2C_RX != 0) if (I2C_RX != 0)
i2c_input_data_type = 0; i2c_input_data_type = 0;
end end
else if (I2C_COUNTER == 4) begin else if (I2C_COUNTER == 2) begin
if (i2c_input_data_type == 5) begin if (i2c_input_data_type == 5) begin
case (I2C_RX) 0: i2c_input_data_type = 5; 16: i2c_input_data_type = 6; case (I2C_RX) 0: i2c_input_data_type = 5; 16: i2c_input_data_type = 6;
32: i2c_input_data_type = 7; default: i2c_input_data_type = 0; endcase 32: i2c_input_data_type = 7; default: i2c_input_data_type = 0; endcase
end end
end end
else if (I2C_COUNTER == 5) begin else if (I2C_COUNTER == 3) begin
if (((i2c_input_data_type == 5) && (I2C_RX != 1)) || ((i2c_input_data_type == 6) && (I2C_RX != 2)) || ((i2c_input_data_type == 7) && (I2C_RX != 3))) if (((i2c_input_data_type == 5) && (I2C_RX != 1)) || ((i2c_input_data_type == 6) && (I2C_RX != 2)) || ((i2c_input_data_type == 7) && (I2C_RX != 3)))
i2c_input_data_type = 0; i2c_input_data_type = 0;
end end
else if (I2C_COUNTER == 6) begin else if (I2C_COUNTER == 4) begin
if (i2c_input_data_type == 4) if (i2c_input_data_type == 4)
temp_output_report = I2C_RX; temp_output_report = I2C_RX[2:0];
else if (((i2c_input_data_type == 6) || (i2c_input_data_type == 7)) && (I2C_RX != 6)) else if (((i2c_input_data_type == 6) || (i2c_input_data_type == 7)) && (I2C_RX != 6))
i2c_input_data_type = 0; i2c_input_data_type = 0;
end end
else if (I2C_COUNTER == 7) begin else if (I2C_COUNTER == 5) begin
if (((i2c_input_data_type == 6) || (i2c_input_data_type == 7)) && (I2C_RX != 0)) if (((i2c_input_data_type == 6) || (i2c_input_data_type == 7)) && (I2C_RX != 0))
i2c_input_data_type = 0; i2c_input_data_type = 0;
end end
else if (I2C_COUNTER == 10) begin else if (I2C_COUNTER == 8) begin
if (i2c_input_data_type == 7) if (i2c_input_data_type == 7)
temp_output_report = I2C_RX; temp_output_report = I2C_RX[2:0];
end end
end end
else begin // I2C_TO_HOST else begin // I2C_TO_HOST
if (I2C_OUTPUT_TYPE == 3) begin if (I2C_OUTPUT_TYPE == 2/*3*/) begin
//if ((I2C_COUNTER < 2) || (I2C_COUNTER > (2 + 10 - 1))) if (I2C_COUNTER == 0) begin
// I2C_TX_REPORT <= 0;
/*else */if (I2C_COUNTER == 2) begin
if (ring_rd != ring_wr) if (ring_rd != ring_wr)
ring_rd = ring_rd + 1; ring_rd = ring_rd + 1;
report_data_radr = ring_rd * 10;
end
else
report_data_radr = report_data_radr + 1;
//else if (I2C_COUNTER == 2)
// I2C_TX_REPORT <= 10;
//else if ((I2C_COUNTER == 3) || (I2C_COUNTER == 5)) begin
// I2C_TX_REPORT <= 0;
// if (ring_rd != ring_wr)
// ring_rd = ring_rd + 1;
//report_data_radr = ring_rd * 10; //report_data_radr = ring_rd * 10;
//end
/*else if (I2C_COUNTER == 4)
I2C_TX_REPORT <= kbd_report[0];*/
//else begin
// I2C_TX_REPORT = report_data_rd;
// report_data_radr = report_data_radr + 1;
//I2C_TX_REPORT <= kbd_report[I2C_COUNTER - 5];
//end
end end
//else //else
// I2C_TX_REPORT <= 0; // report_data_radr = report_data_radr + 1;
end
end end
last_wr = I2C_WR; UART_WR <= 0;
if (I2C_COUNTER != 127)
I2C_COUNTER = I2C_COUNTER + 1;
end // I2C NEW BYTE TX/RX - END end // I2C NEW BYTE TX/RX - END
else if ((last_wr == 1) && (I2C_WR == 0)) begin // I2C_NEW_BYTE_NEGEDGE_FOR_UART else if ((last_wr == 1) && (I2C_WR == 0)) begin // I2C_NEW_BYTE_NEGEDGE_FOR_UART
@ -208,79 +199,66 @@ module top (input CLK, output LED1, LED2, LED3, LED4, LED5,
UART_TX_DATA = I2C_RX; UART_TX_DATA = I2C_RX;
else else
UART_TX_DATA = I2C_TX; UART_TX_DATA = I2C_TX;
last_wr = I2C_WR; //UART_TX_DATA = I2C_COUNTER;
end // I2C_NEW_BYTE_NEGEDGE_FOR_UART - END end // I2C_NEW_BYTE_NEGEDGE_FOR_UART - END
else if ((last_trans == 0) && (I2C_TRANS == 1)) begin // I2C_START_CONDITION OR REPEAT START (UART FF) // ---------------------- I2C START/STOP CONDITIONS, START - ONLY UART FF TX, STOP - ALL LOGIC ----------------- //
if ((last_trans == 0) && (I2C_TRANS == 1)) begin // I2C_START_CONDITION OR REPEAT START (UART FF)
i2c_input_data_type = 0; // UNKNOWN DATA IN i2c_input_data_type = 0; // UNKNOWN DATA IN
uart_double_ff = 1;
UART_TX_DATA = 8'hFF; UART_TX_DATA = 8'hFF;
UART_WR = 1; UART_WR = 1;
last_trans = I2C_TRANS; I2C_COUNTER = 0;
end // I2C_START_CONDITION (UART FF) - END end // I2C_START_CONDITION (UART FF) - END
else if ((last_trans == 1) && (I2C_TRANS == 0)) begin // I2C_STOP CONDITION (OR REPEAT START DETECTED) else if ((last_trans == 1) && (I2C_TRANS == 0)) begin // I2C_STOP CONDITION (OR REPEAT START DETECTED)
KBD_FREEZE <= 0; //KBD_FREEZE <= 0;
if (I2C_READ == 0) begin // DECODING PACKET RECEIVED FROM HOST if (I2C_READ == 0) begin // DECODING PACKET RECEIVED FROM HOST
if (((i2c_input_data_type < 4) && (I2C_INPUT_LEN != 2)) || ((i2c_input_data_type == 4) && (I2C_INPUT_LEN != 5)) || ((i2c_input_data_type == 5) && (I2C_INPUT_LEN != 4)) || ((i2c_input_data_type == 6) && (I2C_INPUT_LEN != 6)) || ((i2c_input_data_type == 7) && (I2C_INPUT_LEN != 9))) if (((i2c_input_data_type < 4) && (I2C_COUNTER != 2)) || ((i2c_input_data_type == 4) && (I2C_COUNTER != 5)) || ((i2c_input_data_type == 5) && (I2C_COUNTER != 4)) || ((i2c_input_data_type == 6) && (I2C_COUNTER != 6)) || ((i2c_input_data_type == 7) && (I2C_COUNTER != 9)))
i2c_input_data_type = 0; i2c_input_data_type = 0;
if ((i2c_input_data_type == 1) || (i2c_input_data_type == 2) || (i2c_input_data_type == 3)) if ((i2c_input_data_type == 1) || (i2c_input_data_type == 2) || (i2c_input_data_type == 3))
I2C_OUTPUT_TYPE = i2c_input_data_type; I2C_OUTPUT_TYPE = i2c_input_data_type - 1;
else if ((i2c_input_data_type == 4) || (i2c_input_data_type == 7)) else if ((i2c_input_data_type == 4) || (i2c_input_data_type == 7))
KBD_LED_STATUS = temp_output_report; KBD_LED_STATUS = temp_output_report;
else if (i2c_input_data_type == 6) else if (i2c_input_data_type == 6)
I2C_OUTPUT_TYPE = 3; I2C_OUTPUT_TYPE = 2;//3;
else if (i2c_input_data_type == 5) else if (i2c_input_data_type == 5)
rststate <= 4'h0; // RESET COMMAND rststate <= 4'h0; // RESET COMMAND
if ((I2C_OUTPUT_TYPE == 1) || (I2C_OUTPUT_TYPE == 2)) if ((I2C_OUTPUT_TYPE == 1) || (I2C_OUTPUT_TYPE == 0))//2))
I2C_OUT_DESC_MASK = 8'hFF; I2C_OUT_DESC_MASK = 8'hFF;
else else
I2C_OUT_DESC_MASK = 8'h00; I2C_OUT_DESC_MASK = 8'h00;
end // END OF I2C_READ == 0 end // END OF I2C_READ == 0
else begin else begin
if (((I2C_OUTPUT_TYPE == 3) /*|| (I2C_OUTPUT_TYPE == 0)*/) && (I2C_INPUT_LEN > 1)) begin if ((I2C_OUTPUT_TYPE == 2/*3*/) && (I2C_COUNTER > 1)) begin
// DEACTIVATING INTERRRUPT IF HOST READ INPUT REPORT (LEN 10) AFTER INTERRUPT OR EMPTY DATA (>=2 BYTES) AFTER RESET // DEACTIVATING INTERRRUPT IF HOST READ INPUT REPORT (LEN 10) AFTER INTERRUPT OR EMPTY DATA (>=2 BYTES) AFTER RESET
//if (ring_rd == ring_wr)
INT = 1; INT = 1;
int_tmr = 0; int_tmr = 0;
//if (ring_rd != ring_wr)
// ring_rd = ring_rd + 1;
end end
I2C_OUTPUT_TYPE = 3; I2C_OUTPUT_TYPE = 2;//3;
I2C_OUT_DESC_MASK = 0; I2C_OUT_DESC_MASK = 0;
end end
last_trans = I2C_TRANS; UART_WR <= 0;
//last_trans = I2C_TRANS;
end // I2C_STOP CONDITION (OR REPEAT START DETECTED) - END end // I2C_STOP CONDITION (OR REPEAT START DETECTED) - END
else if ((last_uart_active == 1) && (UART_ACTIVE == 0)) begin // ---------------- INTERRUPT TO HOST GENERATING LOGIC: DELAY AND INTERRUPT GENERATING (IF NEED) --------------- //
if (uart_double_ff == 1) begin
UART_WR = 1;
UART_TX_DATA = 8'hFF;
uart_double_ff = 0;
end
last_uart_active = UART_ACTIVE;
end
else if ((last_uart_active == 0) && (UART_ACTIVE == 1))
last_uart_active = UART_ACTIVE;
else if (UART_WR == 1) //if (int_tmr != ((1<<(INTERRUPT_TMR_REFLESH+1))-1))
UART_WR = 0; if (int_tmr[INTERRUPT_TMR_REFLESH] != 1)
else if (int_tmr != ((1<<(INTERRUPT_TMR_REFLESH+1))-1))//[INTERRUPT_TMR_REFLESH] != 1)
int_tmr = int_tmr + 1; int_tmr = int_tmr + 1;
else if (/*(int_tmr[INTERRUPT_TMR_REFLESH] == 1) &&*/ (I2C_OUTPUT_TYPE == 3) && (I2C_TRANS == 0)) begin else if ((I2C_OUTPUT_TYPE == 2/*3*/) && (I2C_TRANS == 0)) begin
if (ring_rd != ring_wr) if (ring_rd != ring_wr)
INT = 0; INT = 0;
end end
/*else if (wr_cnt != 0) begin
ring_report[ring_wr * 8 + wr_cnt] <= kbd_report[ (8 * wr_cnt + 7) : (8 * wr_cnt + 0) ]; last_trans <= I2C_TRANS;
wr_cnt = wr_cnt + 1; last_wr <= I2C_WR;
// if (wr_cnt == 0) // START ISR last_isr <= ISR;
end*/ end // END OF NON RESET AND NON INIT LOGIC
end end

5
i2c_keyboard/uart.v
Unescape View File

@ -22,9 +22,10 @@ initial begin
tx_line = 1; tx_line = 1;
end end
always @ (posedge CLK) begin always @ (negedge CLK) begin
if (RESET == 0) begin if (RESET == 0) begin
/*tx_data = 0;*/ tx_clk_counter = 0; /*tx_data = 0;*/ //tx_clk_counter = 0;
tx_activity = 0;
end end
else begin else begin

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