Update i2c_keyboard

master
Ivan Olenichev 6 years ago
parent df04ce9839
commit 61f1fd3bd4

@ -0,0 +1,7 @@
*.dblite
*.ini
*.asc
*.bin
*.blif
*.ex
*.json

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@ -1,9 +1,19 @@
rot.bin: top.v inouts.pcf
default: top.v inouts.pcf
yosys -q -p "synth_ice40 -blif i2c_kbd_alt.blif" top.v i2c_slave.v matrix_kbd.v ram.v simple_filter.v uart.v descriptors.v
arachne-pnr -p inouts.pcf i2c_kbd_alt.blif -o i2c_kbd_alt.txt
icebox_explain i2c_kbd_alt.txt > i2c_kbd_alt.ex
icepack i2c_kbd_alt.txt i2c_kbd_alt.bin
arachne-pnr -d 1k -P tq144 -p inouts.pcf i2c_kbd_alt.blif -o i2c_kbd_alt.asc
# yosys -p "synth_ice40 -json i2_kbd_alt.json" top.v i2c_slave.v matrix_kbd.v ram.v simple_filter.v uart.v descriptors.v
# nextpnr-ice40 --hx1k --json i2_kbd_alt.json --pcf inouts.pcf --asc i2c_kbd_alt.asc
icebox_explain i2c_kbd_alt.asc > i2c_kbd_alt.ex
icepack i2c_kbd_alt.asc i2c_kbd_alt.bin
nextpnr: top.v inouts.pcf
# yosys -q -p "synth_ice40 -blif i2c_kbd_alt.blif" top.v i2c_slave.v matrix_kbd.v ram.v simple_filter.v uart.v descriptors.v
# arachne-pnr -p inouts.pcf i2c_kbd_alt.blif -o i2c_kbd_alt.asc
yosys -p "synth_ice40 -json i2_kbd_alt.json" top.v i2c_slave.v matrix_kbd.v ram.v simple_filter.v uart.v descriptors.v
nextpnr-ice40 --hx1k --json i2_kbd_alt.json --pcf inouts.pcf --asc i2c_kbd_alt.asc
icebox_explain i2c_kbd_alt.asc > i2c_kbd_alt.ex
icepack i2c_kbd_alt.asc i2c_kbd_alt.bin
clean:
rm -f i2c_kbd_alt.blif i2c_kbd_alt.txt i2c_kbd_alt.ex i2c_kbd_alt.bin
rm -f i2c_kbd_alt.blif i2c_kbd_alt.asc i2c_kbd_alt.ex i2c_kbd_alt.bin i2_kbd_alt.json

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System - linux xubuntu 16.04
How to install apio-atom-ide (FPGA programming tool with GUI - atom):
https://github.com/FPGAwars/apio-ide/wiki
Don't forget about command: apio drivers --ftdi-enable
How to install project IceStorm (for manual build FPGA firmware with makefile):
http://www.clifford.at/icestorm/
Test programs (I2C HID host emulator and program for display debug information from FPGA):
Qt5 is installing with nextpnr (part of IceStorm).
Need to install (sudo apt-get update and sudo apt-get install):
qtcreator
libqt5serialport5
libqt5serialport5-dev

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@ -8,7 +8,7 @@ module i2c_slave (input CLK, input RESET,
// RECEIVED BYTES MUST READ WHEN WR POSEDGE, ADRESS NOT READING ###AND BYTE COUNTER >=1 (BYTE COUNTER = 0 - ADRESS)
// BYTES TO TRANSMIT MUST WRITE WHEN WR POSEDGE, BYTE COUNTER CAN BE ZERO
// (FIRST BYTE TRANSMITTED AFTER ADRESS).
// LAST BYTE HAS NO WR ####BUT LAST BYTE NOT TRANSMITTED (DECAUSE MASTER STOPS TRANSMIT)
// LAST BYTE HAS NO WR ####BUT LAST BYTE NOT TRANSMITTED (BECAUSE MASTER STOPS TRANSMIT)
parameter I2C_ADRESS = 7'h34;
parameter MAX_I2C_TRANSACTION_EXP2 = 8; // !!! - FOR LIMIT BYTES TO TX/RX (WITH ADRESS)

@ -5,11 +5,16 @@ module matrix_kbd (input CLK, input RESET, input FREEZE, inout [15:0] ROWS, inpu
// # - LSHIFT (E1), 9 - C (06), 6 - V (19), 3 - DELETE (4C)
// D - LCTRL (E0), C - LALT (E2), B - SPACE (2C), A - RGUI (E7)
parameter ONE_ROW_TIME = 12000;
parameter ROW_STT_PROCESS_TIME = 11000;
parameter ONE_ROW_TIME = 8000;
parameter ROW_STT_PROCESS_TIME = 7000;
parameter ONE_COLUMN_PROCESS_TIME = 50;
parameter ONE_ROW_TIME_POW = 12; // 15 - 65536 tacts or 5.46 ms, 14 - 32768 tacts or 2.73 ms, 13 - 16384 tacts or 1.36 ms,
// 12 - 8191 tacts or 683 mks, 11 - 4096 tacts or 341 mks, 10 - 2048 tacts or 171 ms, 9 - 1024 tacts or 85 mks, 8 - 512 tacts or 43 ms,
// 7 - 256 tacts or 21 mks, other values have no guaranties
parameter ONE_CALC_TIME_POW = 4; // 3 - 16 tacts or 1.3 mks, 4 - 32 tacts or 2.7 mks, 5 - 64 tacts or 5.3 mks, 6 - 128 tacts or 10.7 mks
// ONE_ROW_TIME_POW > (ONE_CALC_TIME_POW - 3); ONE_CALC_TIME_POW > 2 (if 2 or smaller, top module overrun may occur)
reg [15:0] row_time = 0;
reg [12:0] row_time = 0;
reg [3:0] row_counter;
reg [7:0] temp;
@ -31,11 +36,12 @@ module matrix_kbd (input CLK, input RESET, input FREEZE, inout [15:0] ROWS, inpu
reg [8:0] ram_adr;
wire [7:0] ram_rd;
reg [3:0] init_delay_cnt;
reg [8:0] init_ram_cnt;
always @ (negedge CLK) begin
/*always @ (negedge CLK) begin
COLS_SHADOW <= COLUMNS;
end
end*/
ram RAM (CLK, ram_wr, ram_adr, temp, ram_adr, ram_rd);//module ram(input clk, wen, input [8:0] addr, input [7:0] wdata, output [7:0] rdata);
@ -44,36 +50,56 @@ module matrix_kbd (input CLK, input RESET, input FREEZE, inout [15:0] ROWS, inpu
for (i = 0; i < 6; i = i + 1)
report[i] = 0;
isr = 0;
init_delay_cnt = 0;
init_ram_cnt = 0;
row_time = 0;
end
else begin
if (FREEZE == 0) begin
if (init_ram_cnt < 256) begin
if (init_delay_cnt != 15)
init_delay_cnt = init_delay_cnt + 1;
else if (init_ram_cnt < 256) begin
ram_wr = 1;
ram_adr = init_ram_cnt;
temp = 255;
init_ram_cnt = init_ram_cnt + 1;
end
else if (init_ram_cnt == 256) begin
/*else if (init_ram_cnt == 256) begin
ram_wr = 0;
init_ram_cnt = init_ram_cnt + 1;
end
end*/
else begin
if (row_time == ONE_ROW_TIME) begin
row_time = row_time + 1;
if (row_time == 0) begin//== ONE_ROW_TIME) begin
ram_wr = 0;
row_time <= 0;
//row_time <= 0;
row_counter = row_counter + 1;
ROWS_EN = 1 << row_counter;
ram_adr = row_counter;
end
else
row_time <= row_time + 1;
// ROW 0 - D, 1 - A, 2 - C, 3 - B
if (row_time == (ROW_STT_PROCESS_TIME - 1))
/*if (row_time == (ROW_STT_PROCESS_TIME - 1)) begin
temp = ram_rd;
if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 7 + 1))
ram_wr = 1;
if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 0))
COLS_SHADOW <= COLUMNS;
end*/
//if (row_time == 8191/*(ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 7 + 1)*/)
// ram_wr = 1;
if ((row_time[12:8] == 31) && (row_time[4:0] == 0)) begin
//temp = ram_rd;
//COLS_SHADOW = COLUMNS;
if (row_time[7:5] == 0) begin
temp = ram_rd;
COLS_SHADOW = COLUMNS;
end
check_column (row_time[7:5]);
if (row_time[7:5] == 7)
ram_wr = 1;
end
else
kbd_code = 255;
/*if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 0))
check_column (0);
else if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 2))
check_column (2);
@ -90,15 +116,17 @@ module matrix_kbd (input CLK, input RESET, input FREEZE, inout [15:0] ROWS, inpu
else if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 7))
check_column (7);
else
kbd_code = 255;
kbd_code = 255;*/
// START PACK I2C_HID REPORT
if (kbd_code_hid != 0) begin
if ((kbd_code_hid > 8'hDF) && (kbd_code_hid < 8'hE8)) begin
if (kbd_code_hid[7:3] == 5'b11100) begin
//if ((kbd_code_hid > 8'hDF) && (kbd_code_hid < 8'hE8)) begin
if (is_pressed)
report [0] = report [0] | (1<<(kbd_code_hid & 8'h07));
else
report [0] <= report [0] & (~(1<<(kbd_code_hid & 8'h07)));
isr = 1;
end
else begin
if (is_pressed) begin

@ -1,5 +1,5 @@
module ram(input clk, wen, input [8:0] waddr, input [7:0] wdata, input [8:0] raddr, output [7:0] rdata);
reg [7:0] mem [0:255];
reg [7:0] mem [511:0];
reg [7:0] r_data;
reg [7:0] w_data;
reg [7:0] w_addr;

@ -4,6 +4,8 @@ module top (input CLK, output LED1, LED2, LED3, LED4, LED5,
input COM_RX, output COM_TX, COM_DCD, COM_DSR, COM_RTS,
input [7:0] KBD_COLUMNS, inout [15:0] KBD_ROWS);
parameter INTERRUPT_TMR_REFLESH = 14; // 14 - 2^14=16384 tacts or 1.37 ms, 19 - 2^19=524288 tacts or 43.7 ms, 23 - 2^23=8388608 tacts or 0.7 s
// 23 - 1119 LCs, 14 - 1081 LCs (in commit 1b6fc60221b595c2a0f69509d29b6e5c3110feb0)
wire RESET;
reg [3:0] rststate = 0;
@ -31,7 +33,7 @@ module top (input CLK, output LED1, LED2, LED3, LED4, LED5,
wire [7:0] kbd_report [6:0];
wire ISR;
reg INT = 1; // INTERRUPT LINE TO HOST
reg [19:0] int_tmr;
reg [INTERRUPT_TMR_REFLESH:0] int_tmr;
reg KBD_FREEZE = 1; // LOGIC REG FOR BLOCK KBD ACTIVITY WHEN I2C IS WORKING
//reg IS_EMPTY_REPORT = 0; // REGISTER FOR CORRECT START (HOST MUST REQUEST EMPTY REGISTER AFTER INTERRUPT. THEN INTERRRUPT SET TO 1)
matrix_kbd KEYBOARD (CLK, RESET, 0 /*KBD_FREEZE*/, KBD_ROWS, KBD_COLUMNS, kbd_report[0], kbd_report[1], kbd_report[2], kbd_report[3], kbd_report[4], kbd_report[5], kbd_report[6], ISR);
@ -267,10 +269,10 @@ module top (input CLK, output LED1, LED2, LED3, LED4, LED5,
else if (UART_WR == 1)
UART_WR = 0;
else if (int_tmr[19] != 1)
else if (int_tmr != ((1<<(INTERRUPT_TMR_REFLESH+1))-1))//[INTERRUPT_TMR_REFLESH] != 1)
int_tmr = int_tmr + 1;
else if ((int_tmr[19] == 1) && (I2C_OUTPUT_TYPE == 3) && (I2C_TRANS == 0)) begin
else if (/*(int_tmr[INTERRUPT_TMR_REFLESH] == 1) &&*/ (I2C_OUTPUT_TYPE == 3) && (I2C_TRANS == 0)) begin
if (ring_rd != ring_wr)
INT = 0;
end

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